Signal generator, radar device
a signal generator and radar technology, applied in the direction of oscillator generators, instruments, measurement devices, etc., can solve problems such as difficulty in suppressing phase nois
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first embodiment
(Operations of First Embodiment)
[0038]Subsequently, operations of the signal generating circuit 1 according to the first embodiment are described with reference to FIG. 3. FIG. 3 illustrates a transfer function of the signal generating circuit 1 illustrated in FIG. 1. In FIG. 3, a symbol φFMCW is a phase noise of the FMCW signal, a symbol “φR” is a phase noise of the reference signal Ref, a symbol “φnR” is a phase noise of the reference signal, a symbol “N” is a frequency division number of the frequency divider 10, a symbol “φnTDC” is a quantization noise generated at the digital phase detector 15, a symbol “HLPF” is a transfer function of the LPF35, a symbol “Dgain” is a product of a gain of the variable gainer 40 and a gain of the multiplier 45, a symbol “KDAC” is a gain of the current output DAC50, a symbol “φnDAC” is a quantization noise generated at the current output DAC50, a symbol “Ks” is a gain of the integrator 55, a symbol “fref” is a frequency of the reference signal, a...
second embodiment
(Second Embodiment)
[0046]Next, a signal generating circuit according to a second embodiment is described in detail with reference to FIGS. 4, 5A to 5D. As illustrated in FIG. 4, a signal generating circuit 2 of the second embodiment is the one in which a control loop of a gain calibration is added to the signal generating circuit 1 of the first embodiment. In the following description, common reference numerals are used to designate elements common to the signal generating circuit of the first embodiment, and redundant descriptions are not given.
[0047]As illustrated in FIG. 4, the signal generating circuit 2 of the second embodiment includes a differentiator 60 performing a differential process of the frequency setting code output by the code generator 25, and a gain calculator 65 calculating a ratio between the differentiation result and the digital error information input to the current output DAC50 and providing the calculation result for the multiplier 45, in addition to the sig...
third embodiment
(Third Embodiment)
[0059]Next, a signal generating circuit according to a third embodiment is described with reference to FIG. 8. As illustrated in FIG. 8, a signal generating circuit 3 of this embodiment is the one in which the control loop of the gain calibration in the signal generating circuit 2 of the second embodiment is changed. In the following description, common reference numerals are used to designate elements common to the signal generating circuits of the first and second embodiments, and redundant descriptions are not given.
[0060]As illustrated in FIG. 8, the signal generating circuit 3 of the third embodiment includes an integrator 70 and an adder 75 in addition to the elements of the signal generating circuit 1 illustrated in FIG. 1. Besides, the signal generating circuit 3 of this embodiment includes a code generator 26 instead of the code generator 25.
[0061]The code generator 26 in the signal generating circuit 3 of this embodiment outputs a fixed value of the frequ...
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