Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and integrated circuits

Abstract

Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided. A method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir. Annealing extends the interfacial oxide layer into the semiconductor substrate at portions of the semiconductor substrate that underlie the oxygen reservoir to form a regrown interfacial region in or on the semiconductor substrate.

Description

TECHNICAL FIELD[0001]The technical field generally relates to methods of scaling a thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming integrated circuits, and integrated circuits. More particularly, the technical field relates to methods of scaling a thickness of an interfacial oxide layer that enables selective regrowth of the interfacial oxide layer.BACKGROUND[0002]Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel and that is separated from the channel by a gate dielectric structure. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel ...

AI Technical Summary

Benefits of technology

This patent describes methods for scaling the thickness of a gate dielectric structure in integrated circuits. These methods involve forming an interfacial oxide layer and a high-k dielectric layer over a semiconductor substrate, followed by the addition of an oxygen reservoir and a sealant layer. The semiconductor substrate is then annealed to diffuse oxygen through the layers and form a regrown interfacial region in the substrate. This results in a thicker layer of the gate dielectric structure in certain areas, which can improve the performance of the integrated circuit. The patent also provides methods for forming an integrated circuit using these techniques. Ultimately, the patent aims to provide a more efficient and effective way of producing integrated circuits.

Problems solved by technology

However, further scaling of Tinv often results in poor reliability of the resulting FETs, with leakage current through the gate dielectric structure increasing exponentially with the decrease in the Tinv.

However, nitridation of the interfacial oxide layer negatively impacts reliability of P-type FETs, where negative bias temperature instability (NBTI) is a function of nitrogen in the gate dielectric structure.

However, interfacial oxide layer regrowth also occurs at locations of the N-type FETs, thereby negating the benefits of nitridation on Tinv scaling for the N-type FETs.

Further, annealing in the oxygenated environment may also adversely impact dielectric properties of the high-k dielectric layer.

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