Content addressable memory (CAM) devices that perform pipelined multi-cycle look-up operations using cam sub-arrays and longest match detection

Abstract

A CAM system is provided for determining which data word in a CAM array exhibits the longest continuous, unmasked match with an input data value. The input data value is divided into non-overlapping subfields, thereby creating a series of keys, the first key of the series including either the least significant bit (LSB) or most significant bit (MSB) of the input data value. The CAM array is divided along columns into a similar series of non-overlapping sub-arrays corresponding to the subfields defined by the series of keys. A first CAM sub-array compares the first key with its stored rows of data bit values to generate a first match signal. The first match signal disables each row of the second CAM sub-array for which the corresponding row of the first CAM sub-array did not show a match. A second CAM sub-array then compares the second key with its enabled rows to generate a second match signal. The second match signal disables each row of the third CAM sub-array for which the corresponding row of either the first or second CAM sub-array did not show a match. This comparison process continues in sequence with the remaining keys and CAM sub-arrays. The row of the CAM array that shows a match over the most consecutive comparison operations contains the longest match for the input data value. If multiple rows match over the same number of comparison operations, a priority encoder determines which location has the highest priority.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to content addressable memory (CAM) systems. More specifically, the present invention relates to methods and structures for performing a longest match operation in a CAM system.[0003]2. Discussion of Related Art[0004]CAM cells are defined as memory cells that are referenced in response to their content, rather than by a physical address in an array. FIG. 1 shows a block diagram of a conventional CAM array 100 including twelve CAM cells, three match lines ML0-ML2, four data lines DL0-DL3, four complementary data lines DL0#-DL3#, and a splitter 110. A CAM array is specified by a depth, equal to its number of rows, and a width, equal to its number of columns that define the number and length, respectively, of words that can be stored in the array. For example, CAM array 100 has a depth of three bits (three rows) and a width of four bits (four columns) and is therefore a 3×4 array capable of st...

AI Technical Summary

Benefits of technology

[0021]At the same time, because each key is compared only to the corresponding subfields of the stored words, multiple copies of mask registers and match logic circuits are not required. This greatly simplifies the circuit design and reduces hardware costs compared with CAM system 300 shown in FIG. 3.

Problems solved by technology

However, some of the bits of a row may match the input data value, while other bits of the row do not match the input data value.

This can often have undesirable effects at the system level.

However, CAM system 300 includes multiple mask logic blocks, multiple first-level priority encoders, multiple no-match decoders, and additional match logic (i.e., a second level priority encoder), which greatly increases hardware requirements of CAM system 300, increasing circuit size, complexity and cost.

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