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A fast divider with divisor 15í‡2n

A device and fast technology, applied in the field of fast dividers, can solve the problems of slow operation speed, complex structure and many components, and achieve the effect of less components, low cost and simple structure

Inactive Publication Date: 2007-10-10
HEBEI UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention solves the problems of complex structure, many components and slow operation speed in the existing divider technology, thereby providing a divisor with a divisor of 15×2 n Fast divider for , where n is an integer of 0, 1, 2, 3, ... n

Method used

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  • A fast divider with divisor 15í‡2n
  • A fast divider with divisor 15í‡2n
  • A fast divider with divisor 15í‡2n

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0024] The dividend is 0~127×2 n +2 n -1, the divisor is 15×2 n , a divider with fast operation when n=0. Its circuit connection relationship is shown in Figure 1. I1, I2, I3, I4, I5, I6, and I7 are the input terminals of the divider, which constitute the binary dividend I1I2I3I4I5I6I7; I1, I2, I3, I4, I5, I6, and I7 are connected to the Y3 pin and Y2 pin of the adder ADD435 in turn , Y1 pin, X4 pin, X3 pin, X2 pin, X1 pin; I1, I2, and I3 are simultaneously connected to the adder ADD314 in sequence 1 The X3 pin, X2 pin, X1 pin of ADD435; the output F1 pin, F2 pin, F3 pin, F4 pin of the ADD435 are connected to the X1 pin, X2 pin, X3 pin, X4 pin of the adder ADD414 in turn, and the input 1 of the AND gate A2 , 2, 3, 4 pins are connected; the output F5 pin of ADD435 is connected to the adder ADD314 1The Y1 pin of the ADD414; the output pins F1, F2, F3, and F4 of the ADD414 are connected to the 2 pins of the AND gate A6, A5, A4, and A3 in turn, and are connected to the input ...

Embodiment 2

[0034] The dividend is 0~127×2 n +2 n -1, the divisor is 15×2 n , When n=0, the schematic diagram of the divider circuit for fast operation is shown in Figure 2. Its circuit connection relationship is that I1, I2, I3, I4, I5, I6, and I7 are the input terminals of the divider, which form the binary dividend I1I2I3I4I5I6I7; replace the NAND gate NA with the NOT gate N1. The input pin 1 of the NOT gate N1 is connected with the output pin 5 of the AND gate A2, and is connected with the ADD314 2 The Y1 pin of the N1 is connected; the output pin 2 of the NOT gate N1 is respectively connected with the input pin 1 of the AND gate A3, A4, A5, and A6. The output 3 pin of the OR gate R1 is connected to the O0 pin of the divider; the adder ADD314 2The output terminals F1, F2, and F3 of the divider are connected in turn to the output O3, O2, and O1 of the divider to form the binary quotient O0O1O2O3 of the division result; the output 3 pins of the AND gates A3, A4, A5, and A6 are respe...

Embodiment 3

[0044] The dividend is 0~255, and the divisor is 15×2 n , when n=1, the schematic diagram of the divider circuit of fast operation is as shown in Figure 3, and its circuit connection relationship is to increase a connection line I8 from input to output on the basis of Figure 1 1 -O8 1 . When the ADD435 uses a four-bit binary number plus a four-bit binary number and a five-bit adder, all positions other than the lowest three bits of the second addend are 0. Other circuit connections are the same as in Embodiment 1.

[0045] When I1I2I3I4I5I6I7I8 1 When =(11000111)B=(199)D, because X4, X3, X2, X1 of ADD435 constitute the first addend of ADD435, Y3, Y2, Y1 of ADD435 constitute the second addend of ADD435, the ADD435 like this The first addend is (0011)B, the second addend is (110)B, (0011)B+(110)B=(01001)B, so F5, F4, F3, F2, F1 of ADD435 are respectively 0, 1, 0, 0, 1; ADD435 we use a four-digit binary number plus a four-digit binary number and a five-bit adder to implement...

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Abstract

The invention is a kind of divider whose divisor is 15x2n. The character lies in: it uses different adder, and-gate or not gate to form the divider, the input end is the binary dividend, one output end forms the binary quotient of the dividing result, and another end output the binary remainder of the dividing. The divider can carry on division whose divisor is 15x2n, the dividend is 0-1272n +2n -1, (n=0, 1, 2, 3-n). The divider is simple, the cost is low.

Description

technical field [0001] The invention belongs to a divider in an electronic device, in particular to a divisor whose divisor is 15×2 n A fast divider for , where n is an integer of 0, 1, 2, 3, ... n. Background technique [0002] Among the various operations of digital signal processing, division is the most complex operation with the most potential to be tapped. In general-purpose CPUs and DSPs, a divider is often not specifically implemented with hardware, because the proportion of division in general applications is very small, and the design of the divider is much more complicated than other computing components, so the usual practice It is to write software on the basis of other computing components such as ALU and / or multiplier to form a division subroutine. However, in specific application fields such as number system conversion and data unpacking, the situation is different. If the division operation occupies a considerable proportion, simply using software for divi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/52
Inventor 武金木武优西姚芳李艳汪丽萍
Owner HEBEI UNIV OF TECH