A solution method of data transmission deadlock

Abstract

The solution for data transmission deadlock features the timer set in the data transmission interface. The solution includes the following steps: a. for the data transmission interface to generate the timer starting signal for the timer to begin timing; b. to judge whether the timer reaches its set time, and if yes, to reset the timer, to send interface reset signal to the data transmission interface for resetting and to end the process, or else to go to step c.; c. for the data transmission interface to judge whether the current data transmission is ended, and if yes, to reset the timer and to end the process, or else to return to b. Applying the present invention can solve the deadlock problem in data transmission interface.

Description

Technical field [0001] The present invention relates to data transmission technology, in particular to a method for solving data transmission deadlock. Background technique [0002] ATM Universal Test and Operation Physical Interface (UTOPIA) defines the physical layer (PHY) and upper-layer modules, including the interface between the ATM layer and various management entities. The UTOPIA interface enables various types of physical layers to support a common ATM layer. [0003] Figure 1 is a timing diagram of UTOPIA interface data transmission. In this timing diagram, UTOPIA interface adopts cell-level transmission control. As shown in Figure 1, TxClk is the synchronous clock for the ATM and PHY layers; TxClav is the cell flow control signal from the PHY layer, used to indicate whether the PHY layer buffer can receive new cells; TxData is the data bus, used It carries the data transmitted between the ATM layer and the PHY layer; TxEnb is the transmit enable signal sent by the ATM ...

AI Technical Summary

Problems solved by technology

[0006] However, if the TxEnb signal sent by the ATM layer is disturbed during the process of sending the P44 to P48 bytes at the ATM layer and the invalid state transition occurs, the PHY layer cannot detect the 4 valid clock cycles of the TxEnb signal. The PHY layer will think that the ATM layer has not completed the cell transmission this time, and continues to wait to receive the remaining bytes, so the TxClav signal is always at an invalid level; for the ATM layer, TxEnb is an output signal, and it is impossible to know that the TxEnb signal is interfered , so the ATM layer ends this cell transmission after sending the last 4 bytes, and the ATM layer waits for the TxClav signal of the PHY layer to become valid again before starting the next cell transmission

Therefore, in this case, both the ATM layer and the PHY layer are waiting for the signal from the other party, and the UTOPIA interface is in a suspended state, forming a deadlock, and even causing interruption of communication services and loss of information, seriously affecting the reliability of the system sex

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