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Multichip semiconductor package with chip carrier having down stretched pin

A semiconductor and packaging technology, applied in the field of semiconductor packaging, can solve the problems of weak mechanical strength of packaging colloid, reduction of voids, delamination, etc., and achieve the effect of reducing insufficient filling or air cavity problems and improving fluidity

Inactive Publication Date: 2007-10-24
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the thickness of the overall package becomes thinner (that is, the height of the cavity of the package mold is reduced), many problems will arise in the upper packaging device 1: first, the thickness of the encapsulant 16 of the aforementioned packaging device 1 increases with the thickness of the cavity 192, 193 The reduced height makes the mechanical strength of the encapsulant relatively weak, and the chips 12, 13, chip holder 102, and the encapsulant 16 attached to the surface of the chip holder 102 will be delaminated in the subsequent manufacturing process due to the difference in thermal expansion coefficient of the three. Phenomenon (Delamination), leading to a decline in the quality of finished products
This kind of design will greatly reduce the gap between the chip holder 102' and the lower mold cavity 193' for the resin mold flow to pass through, and cause the flow rate of the lower mold flow 18' to be significantly slower than that of the upper mold flow 17'. 'Quickly wrapping the chip 13' causes a pressure to press the chip holder 102', causing the die pad to tilt (Die Pad Floating), and then presses the pressure to press the die pad 102', causing the die pad to tilt (Die Pad Floating), which indirectly leads to the die pad floating. Lines 14', 15' are exposed outside the encapsulant 16'

Method used

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  • Multichip semiconductor package with chip carrier having down stretched pin
  • Multichip semiconductor package with chip carrier having down stretched pin
  • Multichip semiconductor package with chip carrier having down stretched pin

Examples

Experimental program
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Embodiment 1

[0031] Please refer to FIG. 5 , which is a schematic cross-sectional view of a multi-chip thin semiconductor package according to a first embodiment of the present invention. As shown in the figure, the semiconductor package structure 2 of this first embodiment includes a metal lead frame 20, and at least one supporting frame bar 200 is provided at the central part to carry a plurality of semiconductor chips 22, 23, and the supporting frame bar 200 On the top is formed a plurality of downwardly extending legs 201 integrally connected with the support frame bar 200, which together form a chip carrier 202 with the support frame bar 200; a first chip 22 is pasted on the support frame bar 200 and electrically connected to the multiple pins 203 on the periphery of the support frame bar 200 by a first gold wire group 24; a second chip 23 is bonded to the first chip 22, and a second chip 23 is bonded to the first chip 22, Two gold wire groups 25 are electrically coupled with these pi...

Embodiment 2

[0037] 7 and 8 show a multi-chip thin semiconductor package according to a second embodiment of the present invention. The structure of this embodiment is substantially the same as that of the aforementioned first embodiment, except that the structure 3 of the second embodiment is that more than three semiconductor chips 32 , 33 , 34 , (or even 35 ) are wrapped in a package. Since there is a space between the adjacent extension legs 301 to allow the mold flow to pass through, the chip carrier 302 can be placed as close to the lower mold as possible, relatively leaving more packaging space above the second chip 33 for the third or even the fourth chip 34 ( Or even 35) bonding, thereby significantly doubling the function and speed of the package without increasing the overall height of the package structure.

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Abstract

A multichip semiconductor packaging unit with downward extended stabilizer chip carrier includes a lead frame with a chip carrier at the center which area and width are smaller than that of the chip,in which, the loaded is composed of a strip support frame and several groups of downward extended stabilizers very small carrier will not block the mold flow and eough space between adjacent stabilizers for mold flow passing through can avoid insufficient filling of resin or void, besides, downward stabilizers can be seen as a prestress structure which grasps the die cavity base firmly after closing, and chips will not stricken by the mold flow.

Description

technical field [0001] The present invention relates to a semiconductor package, in particular to a semiconductor package that uses a chip carrier with a plurality of downwardly extending legs instead of a die pad to carry a semiconductor chip. Background technique [0002] Electronic products are developing toward lightness, thinness, shortness, and miniaturization. Semiconductor devices are developing toward low cost, high performance, and small size. Thin Small Outline Package), SSOP (Shrink Small Outline Package) and TQFP (Thin Quad Flat Package) and other thin packaging products with a thickness of only 1 mm, or even 0.75 mm (such as UTSOP (Ultra Thin Small Outline Package)); It is required to install two or more semiconductor chips in a semiconductor device, by increasing integrated circuit density, memory capacity and processing speed. [0003] US Patent No. 5,527,740 discloses a thin semiconductor device with multiple chips. As shown in accompanying drawing 1, this...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/04H01L25/18H01L23/48H01L23/28
CPCH01L2224/48091H01L2224/48247H01L2224/73265H01L2924/00014
Inventor 许进登汤富地游振士洪瑞祥洪进源
Owner SILICONWARE PRECISION IND CO LTD