Multichip semiconductor package with chip carrier having down stretched pin
A semiconductor and packaging technology, applied in the field of semiconductor packaging, can solve the problems of weak mechanical strength of packaging colloid, reduction of voids, delamination, etc., and achieve the effect of reducing insufficient filling or air cavity problems and improving fluidity
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Embodiment 1
[0031] Please refer to FIG. 5 , which is a schematic cross-sectional view of a multi-chip thin semiconductor package according to a first embodiment of the present invention. As shown in the figure, the semiconductor package structure 2 of this first embodiment includes a metal lead frame 20, and at least one supporting frame bar 200 is provided at the central part to carry a plurality of semiconductor chips 22, 23, and the supporting frame bar 200 On the top is formed a plurality of downwardly extending legs 201 integrally connected with the support frame bar 200, which together form a chip carrier 202 with the support frame bar 200; a first chip 22 is pasted on the support frame bar 200 and electrically connected to the multiple pins 203 on the periphery of the support frame bar 200 by a first gold wire group 24; a second chip 23 is bonded to the first chip 22, and a second chip 23 is bonded to the first chip 22, Two gold wire groups 25 are electrically coupled with these pi...
Embodiment 2
[0037] 7 and 8 show a multi-chip thin semiconductor package according to a second embodiment of the present invention. The structure of this embodiment is substantially the same as that of the aforementioned first embodiment, except that the structure 3 of the second embodiment is that more than three semiconductor chips 32 , 33 , 34 , (or even 35 ) are wrapped in a package. Since there is a space between the adjacent extension legs 301 to allow the mold flow to pass through, the chip carrier 302 can be placed as close to the lower mold as possible, relatively leaving more packaging space above the second chip 33 for the third or even the fourth chip 34 ( Or even 35) bonding, thereby significantly doubling the function and speed of the package without increasing the overall height of the package structure.
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