Chip interface detection apparatus and method

Abstract

The invention relates to a chip interface checking device, which comprises an external checking element and an internal checking element, wherein the external one comprises a control unit for sending and comparing the checking signal and checking signal, and an external storage module for storing checking signal, while the external checking signal line is connected between control unit and external storage module; and internal checking element comprises a checking special internal storage unit for storing the checking signal, while the internal storage unit via interface ready checking signal line is connected to the control unit. The invention also discloses a relative checking method. The invention can check any interface signal line, to reduce the cost.

Description

technical field [0001] The invention relates to chip detection technology, in particular to a chip interface detection device and method. Background technique [0002] The currently used chip interface includes at least: address lines, data lines and read-write control lines, usually M address lines, A[1]...A[m]...A[M], 1≤m≤M , the address signal has a total of 2 M There are two kinds of combinations; there are N data lines in total, D[1]...D[n]...D[N], 1≤n≤N, and there are 2 data signals N a combination form. [0003] 1 is a schematic diagram of the composition and structure of a chip interface detection device in the prior art. The chip interface detection device in the prior art includes: an external detection device 101 placed outside the chip 100 and an internal detection device 102 placed inside the chip. [0004] Wherein, the external detection device 101 includes: a control unit 110 for receiving detection instructions and controlling the detection process, and an...

AI Technical Summary

Problems solved by technology

[0012] 1) The inherent storage unit group inside the chip is composed of various types of storage units. The read and write functions of different types of storage units are different. For example, some storage units cannot perform read and write operations, and some storage units are automatically cleared after reading. The control unit cannot perform effective read and write operations on all storage units, resulting in the inability to traverse all combinations of address signals and all combinations of data signals during detection;

[0013] 2) Each detection actually detects an address signal combination and a data signal combination, and the total number of address signal combinations and data signal combinations inside the chip is 2 M+N One, in order to achieve a certain detection coverage of the interface address lines and interface data lines, multiple detections are required, and the detection cost and difficulty are very high;

[0014] 3) In practical application, although the interface data line is directly detected, the interface data line, interface address line and interface control line are used for each detection, so this detection method actually detects a combination of data signals Combined with an address signal, it cannot be specifically detected for the interface data line or interface address line. When an error is detected, it is difficult to determine which signal line the error is generated on.

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