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System and method for achieving fast switching of analog voltages on large capacitive load

A capacitive load and voltage technology, applied in electronic switches, electrical components, digital memory information, etc., to achieve fast response time and reduce noise

Inactive Publication Date: 2008-07-02
SANDISK CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Thus, adding bias current in a buffer to improve response time is generally undesirable

Method used

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  • System and method for achieving fast switching of analog voltages on large capacitive load
  • System and method for achieving fast switching of analog voltages on large capacitive load
  • System and method for achieving fast switching of analog voltages on large capacitive load

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Embodiment Construction

[0034] The present invention is directed to a driver circuit for driving capacitive loads which provides improved response time for driving the load between two or more voltages without increasing the power consumption of the driver circuit.

[0035] Fig. 1 shows a block diagram of an exemplary embodiment of a driving circuit or driver 100 according to the present invention. Referring to FIG. 1, the driver 100 includes a load amplifier or buffer 105 with a signal or input voltage (V IN ) input 110 and an output 115 coupled to a capacitive load 120, the output 115 is used to apply an output voltage (V OUT ). According to the invention, the driver 100 further comprises a reservoir or reserve circuit 125 having: a reserve capacitor 130; a reserve amplifier or buffer 135 for charging the reserve capacitor; a switch 140; and a controller 145 for opening and closing the switch. The reserve buffer 135 is included for receiving signals or input voltages (V RES_IN ) of the input 15...

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PUM

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Abstract

Driver (100) and method are provided for driving capacitive load (120) that achieve an improved response time without increasing power consumption of the driver. Driver (100) has load buffer (105) with an input (110) for receiving an input voltage (VIN), and an output 115 for coupling an output voltage (VOUT) to load 120. VOUT is driven between a first voltage level (V1) and a second voltage level (V2) in response to changes in VIN. Driver (100) also has reserve circuit (125) with capacitor (130), reserve buffer (135), switch (140) for coupling the capacitor to capacitive load (120) and controller (145) for operating the switch. Reserve buffer (135) has an input (150) for receiving an input voltage (VRES-IN), and an output (155) for coupling an output voltage (VRES-OUT) to capacitor (130) to charge the capacitor. Controller (145) is configured to operate switch (140) to couple capacitor (130) to capacitive load (120) when VOUT is being driven between V1 and V2.

Description

technical field [0001] The present invention relates generally to drive circuits for capacitive loads, and more particularly to systems and methods for enabling fast switching of analog voltages on large capacitive loads. Background technique [0002] Conventional drive circuits or drivers for driving capacitive loads typically include a signal input, a signal output, and an amplifier or analog voltage buffer to drive the load between two or more voltages. Two important characteristics of a buffer are power consumption and response time, where response time is the time to reach a specified output after applying a specified input under specified operating conditions. In general, these two properties cannot be optimized at the same time. This is because improving response time means increasing unity-gain frequency and slew rate as well as the amplifier's ability to react quickly at the output to changes in the input, both of which require increasing the buffer's bias current....

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C5/14G11C8/08G11C16/08H03K17/30G11C16/06
CPCG11C5/145G11C8/08G11C16/00
Inventor 杰弗里·S·恭沃沙扎德·克哈利德
Owner SANDISK CORP