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Method and device for supplying fault insertion for logic level

A technology of fault insertion and logic level, which is applied to the detection of faulty computer hardware, measurement devices, logic operation inspection, etc. It can solve the problem of inability to collect and detect the system state, cannot be realized, and cannot conveniently determine whether the fault injection has reached the expected goal and other issues to achieve the effect of improving test efficiency, improving reliability, and ensuring effectiveness

Inactive Publication Date: 2008-07-16
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] 1. It is impossible to pull half-high and pull to the set voltage fault insertion for various logic levels (including LVTTL level, TTL level, LVCMOS level, CMOS level, GTL level)
[0015] 2. It is impossible to collect and detect the system state after fault insertion, so it is impossible to conveniently determine whether the fault injection has achieved the expected goal, but it is necessary to know whether the fault insertion has achieved the expected goal through complicated manual measurement

Method used

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  • Method and device for supplying fault insertion for logic level
  • Method and device for supplying fault insertion for logic level
  • Method and device for supplying fault insertion for logic level

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Embodiment Construction

[0054]The present invention provides a method and device for providing fault insertion for logic levels. The core of the present invention is: using scrambling transistors and adjustable power supplies to pull various digital logic levels to half-high and pull to set according to requirements Voltage fault insertion, and the target system voltage after fault insertion is detected by ADC (analog-to-digital converter), and the fault insertion effect is judged by the board software. If the fault insertion effect is not achieved, the fault synchronization control operation is automatically performed by the board software , until the sampled target system voltage value is equal to the fault voltage value that should be achieved.

[0055] The structural diagram of the device for providing fault insertion for logic levels provided by the present invention is as follows image 3 As shown, it mainly includes four modules: a fault insertion control management module, a digital adjustabl...

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Abstract

Wherein, the said method comprises: using adjustable power to insert fault logic level; sampling the voltage value of inserted target system with an ADC and hereby adjusting the logic level voltage of target system by adjusting former power till the target voltage value equal to value of inserted fault voltage. This invention realizes fault voltage insertion of half-height and set lift voltage, and acquires information to decide the insertion effect.

Description

technical field [0001] The invention relates to the field of electronic product testing, in particular to a method and device for providing fault insertion for logic levels. Background technique [0002] Demand for digital consumer electronics is growing strongly in the market today. However, in the development and testing stages of digital electronic products, there is no effective verification method for the product's fault handling capability. In many cases, it is only after an accident occurs on site that the fault handling mechanism of the system is not perfect. Therefore, in order to detect problems in the system fault handling mechanism as early as possible and improve product reliability, it is urgent to provide perfect fault insertion methods in the laboratory to verify that digital electronic products are in abnormal conditions such as device failure, external interference, and human operation errors. Protection and self-healing ability under certain conditions, i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/38G06F11/25H01T13/60
Inventor 胡雪涛
Owner HUAWEI TECH CO LTD