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Wafer packaging for asymmetric casting mold

A chip packaging, asymmetric technology, applied in the direction of electric solid-state devices, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of general products without structure and inconvenience, and achieve the effect of improving warpage and good reliability

Inactive Publication Date: 2008-11-26
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the conventional small external lead package 100b still has the above-mentioned problems
[0006] It can be seen that the above-mentioned existing chip package obviously still has inconvenience and defects in structure and use, and needs to be further improved urgently.
In order to solve the problems existing in the chip package, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and the general products do not have a suitable structure to solve the above problems, which is obvious. It is a problem that relevant industry players are eager to solve

Method used

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  • Wafer packaging for asymmetric casting mold
  • Wafer packaging for asymmetric casting mold
  • Wafer packaging for asymmetric casting mold

Examples

Experimental program
Comparison scheme
Effect test

no. 2 example

[0074] Figure 3A A top view of an unmolded chip package according to a second embodiment of the present invention is shown, wherein Figure 3A The first bonding wire, the second bonding wire and the encapsulant are not shown. Figure 3B Shown is the fully formed chip package after encapsulation and along the Figure 3A A cross-sectional view of the A-A' line, while Figure 3C Shown is the fully formed chip package after encapsulation and along the Figure 3A The cross-sectional view of the B-B' line. Please refer to Figure 3A to Figure 3B , this embodiment is similar to the first embodiment, the difference is that in this embodiment, the spoiler 314 has a first end 314a and a second end 314b, wherein the first end 314a is connected to the lead frame body 212 connect. In addition, the spoiler 314 is bent downward to form a concave portion 314d, and then bent upward, and the spoiler 314 has a first end 314a and a second end 314b, wherein the second end 314b is higher tha...

no. 3 example

[0079] Figure 4A to Figure 4D A cross-sectional view of a chip package according to a third embodiment of the present invention is shown. Please refer to Figure 4A and Figure 4B The chip package in this embodiment includes a lead frame (not shown), a chip 420, an adhesive layer 430, a plurality of first bonding wires 440a and an encapsulant 450, wherein the lead frame includes a lead frame body 412 and At least one spoiler 414, and the lead frame body 412 has a plurality of inner lead portions 412a, a plurality of outer lead portions 412b and a chip carrier 412c. The chip 420 is disposed on the chip carrier 412c, and the adhesive layer 430 is disposed between the chip 420 and the chip carrier 412c for fixing the chip 420 . These first bonding wires 440a are respectively electrically connected between the chip 420 and the inner lead portion 412a, and the encapsulant 450 at least covers the chip 420, the first bonding wire 440a, the inner lead portion 412a, the adhesive la...

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PUM

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Abstract

The invention relates to the chip package of asymmetry mould, which comprises: one wire support, one chip, one adhesive layer, several packing lines and one packing adhesive, wherein said wire support has one main body and at least one interference plate; the main body has several internal pins and several external pins; the interference plate bends downwards to form one concave while its first end is connected to the main body, and second end is lower than the internal pins; the chip is fixed under the internal pins; the interference plate is at one side of chip; the adhesive layer is between the chip and the internal pins; the packing lines are connected between the internal pins and the chip; the packing adhesive at least covers chip, packing lines, internal pins, adhesive layer and interference plate, while the thickness of said adhesive above the concave and the thickness of said adhesive under the concave are rated higher than 1, and the ratio between the thickness under the external pins and the thickness above the external pins are different.

Description

technical field [0001] The present invention relates to an asymmetrically molded chip package, and more particularly to a chip package with a lead frame. Background technique [0002] For dynamic random access memory (DRAM), the packaging methods used can be divided into small outline J-lead (SOJ) and small outline J-lead (thin small outline package, TSOP), and the advantages of these two types are fast transmission speed, good heat dissipation, and small structure. However, as far as the lead frame is concerned, the small J-type external lead package and the small external lead package can be divided into lead on chip (LOC) packages, such as US Patent 4,862,245 or lead on chip. The pins are located below the chip (chip on lead, COL), eg US Patent 4,989,068. [0003] Figure 1A A cross-sectional view of a conventional small-outline package with an LOC structure is shown. Please refer to Figure 1A As shown, the conventional small external lead package 100a includes a lead...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/495H01L23/488
CPCH01L2224/4826H01L2224/73265H01L2224/32245H01L2224/73215H01L2924/00
Inventor 杜武昌沈更新
Owner CHIPMOS TECH INC