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Semiconductor encapsulation structure and its making method

A packaging structure and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of occupying printed circuit boards, large connection area, and inability to package semiconductor chips, etc. To achieve the effect of improving the electrical function and quality, and enhancing the electrical function

Inactive Publication Date: 2008-12-24
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The common problem with the above packaging structure is that the pins used to electrically connect to external devices such as printed circuit boards protrude out of the encapsulant, so they often occupy a large area of ​​the printed circuit board.
This packaging structure cannot be used to package semiconductor chips with center pads, cross-shaped or I-shaped arrays, such as DRAM chips.
[0012] In addition, passive components cannot be configured in the above-mentioned various packaging structures to improve the electrical function of the packaging structure

Method used

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  • Semiconductor encapsulation structure and its making method
  • Semiconductor encapsulation structure and its making method
  • Semiconductor encapsulation structure and its making method

Examples

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Embodiment 1

[0040] see Figure 5A to Figure 5E , which is a schematic cross-sectional view of Embodiment 1 of the semiconductor package structure and its manufacturing method of the present invention.

[0041] Embodiment 1 of the present invention is mainly described in a batch manner, so as to improve the process efficiency and enable mass production. Of course, it can also be performed in a single wafer manner, and is not limited thereto.

[0042] The manufacturing method of the semiconductor package structure of the present invention includes the following steps. Such as Figure 5A As shown, it provides a substrate module sheet 54A with a plurality of substrates 54, and each of the substrates 54 is formed with at least one opening 541, and the form of the opening 541 is corresponding to the active surface of the semiconductor chip to be packaged subsequently. The layout arrangement of the pads. In this embodiment, the bonding pads on the active surface of the semiconductor chip to b...

Embodiment 2

[0050] Please also refer to FIG. 6A to FIG. 6D , which are schematic cross-sectional views of Embodiment 2 of the semiconductor package structure and its manufacturing method of the present invention.

[0051] The manufacturing method of the semiconductor package of the present invention includes: as shown in FIG. 6A , providing a lead frame 51 with a plurality of pins 511, and each of the pins 511 has an inner edge 511a and an outer edge 511b that form a gap. The height of the outer edge 511b of the pin is greater than the height of the inner edge 511a, and the semiconductor chip 50 is placed on the inner edge 511a of the pin. The semiconductor chip 50 has an active surface 50a and an opposite non-active surface 50b, and the semiconductor chip 50 is connected to the inner edge 511a of the pin with its non-active surface 50b, and the active surface 50a of the semiconductor chip is provided with a welding pad 500 .

[0052] As shown in Figure 6B, a substrate 54 is placed on th...

Embodiment 3

[0057] see also Figure 7 , which is a schematic cross-sectional view of Embodiment 3 of the semiconductor package structure of the present invention.

[0058] Embodiment 3 of the present invention is substantially the same as Embodiment 1 above, the main difference is that the size of the substrate 54 is larger than the size of the semiconductor chip 50, for the semiconductor chip 50 to be placed on the inner edge 511a of the pin 511, and to be connected to the semiconductor chip. The substrate 54 on the lead frame 50 is electrically connected to the pin inner edge 511 a of the lead frame 51 .

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Abstract

The invention discloses a semiconductor package structure and a manufacturing method thereof. The structure comprises a semiconductor chip, a substrate, a bonding wire, a lead frame with multiple pins and a packaging colloid. The semiconductor package structure and its manufacturing method of the present invention can indeed be used to package various semiconductor chips with different pad arrangements, forming a package structure with no protruding pins and having light, thin and short characteristics, and at the same time, it can be used for stacking and connecting of package structures. Set passive components to enhance electrical functions.

Description

technical field [0001] The invention relates to a semiconductor packaging structure and its manufacturing method, in particular to a semiconductor packaging structure with an integrated lead frame and its manufacturing method. Background technique [0002] The traditional thin small outline package (Thin Small Outline Package, TSOP) is mainly to connect the semiconductor chip on a lead frame with multiple pins on both sides, and then use the encapsulant to cover the semiconductor chip, so as to use two The extended part of the side pin is electrically connected with the outside. [0003] Such as figure 1 As shown, it is a schematic cross-sectional view of a traditional TSOP, which includes a lead frame 11, which has a chip holder 111 and a plurality of pins 112 arranged on both sides of the chip holder 111; 111 on the semiconductor chip 10, and the semiconductor chip 10 is electrically connected to the pin 112 by the bonding wire 12; and a packaging compound 13 for coverin...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L23/31H01L21/60H01L21/56
CPCH01L24/97H01L2224/32245H01L2224/48091H01L2224/4824H01L2224/48247H01L2224/4826H01L2224/48455H01L2224/73215H01L2224/97H01L2924/01005H01L2924/01006H01L2924/01015H01L2924/01033H01L2924/01082H01L2924/181H01L2924/18165H01L2924/00014H01L2224/85H01L2924/00012
Inventor 黄建屏张锦煌
Owner SILICONWARE PRECISION IND CO LTD