A non extension method for making high-voltage part groove
A high-voltage device and channel technology, which is applied in the manufacture of semiconductor/solid-state devices, electrical components, circuits, etc., can solve problems such as high cost and complicated production process, and achieve the effect of simplifying the production process and reducing production costs
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Embodiment 1
[0011] a. First produce a sacrificial oxide layer on the surface of the silicon wafer;
[0012] b. Inject about 1500 keV of phosphorus into some areas that require N-type buried layer, such as PMOS, as the N-type buried layer;
[0013] c. Implant phosphorus of about 150 keV in PMOS and other areas that need to be uniformly doped with N-type substrates, and then perform high-temperature and long-term annealing at about 1200 ° C for about 8 hours to achieve quasi-uniformly doped N-type channels.
Embodiment 2
[0015] a. First produce a sacrificial oxide layer on the surface of the silicon wafer;
[0016] b. Inject about 1000 keV of phosphorus into some areas that require N-type buried layer, such as PMOS, as the N-type buried layer;
[0017] c. Implant phosphorus of about 100 keV in some areas such as PMOS that need to be uniformly doped with N-type substrates, and then perform high-temperature and long-term annealing at about 1200 ° C for about 8 hours to achieve quasi-uniformly doped N-type channels.
Embodiment 3
[0019] a. First produce a sacrificial oxide layer on the surface of the silicon wafer;
[0020] b. Inject about 2000 keV of phosphorus into some areas that require N-type buried layer, such as PMOS, as the N-type buried layer;
[0021] c. Implant about 200 keV of phosphorus in PMOS and other areas that need to be uniformly doped with N-type substrates, and then perform high-temperature and long-term annealing at about 1200 ° C for about 8 hours to achieve quasi-uniformly doped N-type channels.
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