Stack type semiconductor packaging structure

Abstract

A stackable semiconductor package structure is provided, which comprises a first substrate, a chip, a low modules film, a second substrate, a plurality of first wires, and a first packaging adhesive. The chip is positioned on the first substrate. The low modules film is positioned on the chip. The second substrate is positioned on the low modules film, and the area of the low modules film can be regulated according to the area of the second substrate, to support the second substrate. The first wire is electrically connected with the first substrate and the second substrate. The first packaging adhesive exposes the partial solder pad of the second substrate. Therefore, during the wire bonding operation, the suspension part of the second substrate doesn't swing or vibrate and the area of the second substrate can be increased to store more elements. Additionally, the thickness of the second substrate can be reduced so s to reduce the total thickness of the stackable semiconductor package structure.

Description

technical field [0001] The invention relates to a stackable semiconductor packaging structure, in particular to a stackable semiconductor packaging structure containing a low modulus film (Low Modules Film). Background technique [0002] Please refer to figure 1 , is a schematic cross-sectional view of a conventional stackable semiconductor package structure. The conventional stackable semiconductor package structure 1 includes a first substrate 11 , a chip 12 , a spacer (Spacer) 13 , a second substrate 14 , a plurality of first wires 15 and a first sealing material 16 . [0003] The first substrate 11 has a first surface 111 and a second surface 112 . The chip 12 has a first surface 121 and a second surface 122, the second surface 122 of the chip 12 is adhered to the first surface 111 of the first substrate 11 by an adhesive layer 17, and the first surface 121 of the chip 12 utilizes a plurality of second wires 18 is electrically connected to the first surface 111 of the...

AI Technical Summary

Problems solved by technology

Firstly, the spacer 13 is a plate body, which is pre-cut to the required size, glued and then adhered to the chip 12, and then the second substrate 14 is adhered to the spacer 13. The above steps are not only complicated, but also difficult to correct. bit

Secondly, the spacer 13 cannot contact the second wire 18, so its area must be smaller than the area of ​​the chip 12. However, since the area of ​​the second substrate 14 will be larger than the area of ​​the chip 12, some parts of the second substrate 14 will extend beyond the spacer. 13, while forming a dangling part

Under normal circumstances, the first pad 143 will be located in the suspended part (that is, the periphery of the spacer 13 or the relative position of the chip 12), and the distance between the first pad 143 and the relative position of the edge of the spacer 13 is defined as the suspension length. L1. Experiments show that when the suspended length L1 is more than three times greater than the thickness T1 of the second substrate 14, the suspended part will shake or vibrate during the wire bonding operation, which is not conducive to wire bonding. Operation

What's more, when the second substrate 14 is subjected to too much downward stress during the wire bonding operation, it will cause the second substrate 14 to crack.

Secondly, because there will be the above shaking, vibration or cracking, the suspended part should not be too long, so that the area of ​​the second substrate 14 is limited, so that the first surface 141 of the second substrate 14 exposed by the sealing opening 19 is limited. The layout space on the second pad 144

Finally, in order to reduce the above shaking, vibration or cracking, the thickness of the second substrate 14 should not be too thin, so the overall thickness of the existing stackable semiconductor package structure 1 cannot be effectively reduced.

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