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Semiconductor device

A technology of semiconductors and devices, which is applied in the field of testing memory chips installed in the above semiconductor devices, and can solve the problem that the test circuit cannot test logic and memory chip interfaces, etc.

Inactive Publication Date: 2009-08-19
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the test circuit cannot test the interface between logic and memory chips used in normal operation

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0114] specific implementation plan

[0115] Embodiments of the present invention will be described below with reference to the accompanying drawings.

[0116] figure 1 A first embodiment of a semiconductor device according to the present invention is shown. By mounting a logic chip 12 and a memory chip 14 on a system wiring board 10, the semiconductor device is formed as a system in package (hereinafter simply referred to as SIP). exist figure 1 , small circles shown near the periphery of the logic chip 12 represent external terminals of the SIP. Logic chip 12 has memory connection terminals (not shown) for connecting to terminals of memory chip 14 . exist figure 1 In , signal lines indicated by bold lines each consist of many signal lines.

[0117] Logic chip 12 has logic circuit 16 which operates simultaneously with clock signal CLK, memory controller 18, memory interfaces 20 and 22, memory test circuit 24, entry circuit 26, external interfaces 28 and 30, memory test ...

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Abstract

A logic chip and a memory chip accessed by the logic chip are mounted in the same package. The pattern generator of the logic chip operates in a first test mode to generate internal test patterns for the memory chip. The mode selector selects an internal test pattern output from the pattern generator in a first test mode, selects an external test pattern provided through the test terminal in a second test mode, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested using an internal test pattern (first test pattern) generated in the logic chip or an external test pattern (second test pattern) provided from the outside according to the mode selection signal.

Description

[0001] This application is a divisional application of Chinese patent application 02120065.3 with a filing date of May 22, 2002. technical field [0002] The present invention relates to a semiconductor device in which many chips are mounted in the same package individually constituting a system, and a semiconductor device mounted in the above semiconductor device. In particular, the present invention relates to a technique of testing a memory chip mounted in the above semiconductor device. [0003] Furthermore, the present invention relates to a technique which provides a clock signal applied to a semiconductor chip constituting the above semiconductor device. Background technique [0004] Recently, packaging techniques have been developed for preparing semiconductor devices in which memory chips, digital chips, analog chips, passive components, etc., each of which is different in processing technology, are packaged in a single package serving as a system. Also, due to the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/36G01R31/28G01R31/3183G01R31/3185G11C11/401G11C11/406G11C11/407G11C29/00G11C29/02G11C29/12
Inventor 山崎雅文铃木孝章中村俊和江渡聪三代俊哉佐藤绫子米田隆之川村典子
Owner SOCIONEXT INC