Electronic data processing circuit that transmits packed words via a bus and the data processing method
A technology for processing circuits and electronic data, applied in the fields of electrical digital data processing, instruments, sustainable buildings, etc., can solve the problems of address/data bus power loss, not giving multiple word packing, reducing execution speed, etc.
Inactive Publication Date: 2009-10-07
KONINKLIJKE PHILIPS ELECTRONICS NV
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Problems solved by technology
In this case, these publications give no basis for packing multiple words into larger words
[0007] In addition to causing potential access conflicts that slow down execution, the address / data bus also causes significant power consumption
Method used
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[0027] figure 1 Represents an electronic circuit comprising a plurality of processors 10a-d, a bus interface 12, a bus 14 and a plurality of memories 16a,b. Each processor 10a-d has an address output A, a data output D and a control input / output. A bus interface 12 connects address and data outputs to a bus 14 to which memories 16a,b are connected to receive address and data information. The bus 14 includes a plurality of address lines, a plurality of n data lines (eg n=64 or n=128 data lines) and control lines.
[0028] For purposes of illustration, processors 10a-d are shown with only data outputs, but it should be understood that they may have data inputs, or data input / outputs, connected to bus interface 12 . Although processors 10a-d are shown, it should be understood that any other type of data processing unit may be used. Similarly, while two memories are shown connected to bus 14 for purposes of illustration, it should be understood that many other circuits may be c...
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An electronic data processing circuit contains a plurality of data handling units (10a-d, 16a-b) with data outputs, at least part of the data handling units having address outputs. The data handling units supply words of preferably selectable size to a bus. A bus controller (20) is arranged to control access to the bus in successive access cycles. The bus controller (20) causes data bits from a plurality of data words from respective ones of the data handling units (10a-d, 16a-b), to be placed in combination on the data lines in a same bus cycle. The bus controller causes write addresses that the respective ones of the data handling units (10a-d, 16a-b) supply for respective ones of the plurality of data words to be placed on the address lines in a plurality of respective bus cycles. Preferably, the temporal or spatial arrangement of the data words on the bus lines adapted so as to minimize the number of logic level changes on the bus.
Description
technical field [0001] The invention relates to an electronic data processing circuit comprising a bus and a plurality of data processing units having access to the bus. Background technique [0002] An address / data bus is a known solution for allowing multiple data processing units to access shared resources, such as memory. Traditionally, each time a data processing unit accesses the bus, it puts the data and the corresponding address on the data line and the address line of the bus respectively. [0003] Modern data buses are very wide, allowing words with multiple bits (eg 64 or 128 bits) to be placed on the bus in one bus cycle. The data processing circuitry does not always use all these bits, since the length of the word that has to be written is often smaller than the maximum word length. For example, 32-bit, or even 16-bit numbers are often used. [0004] US Patent No. 6,366,984 discloses how this redundancy can be used to increase memory bandwidth by packing diff...
Claims
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Login to View More IPC IPC(8): G06F13/16G06F13/36
CPCY02B60/1228G06F13/1678G06F13/36Y02D10/00G06F13/16G06F13/14G06F13/40
Inventor 米林德·M·库尔卡尼比约·托马斯
Owner KONINKLIJKE PHILIPS ELECTRONICS NV