Chip encapsulation structure and technology

Abstract

This invention provides one chip sealing structure, which comprises chip and buffer glue, wherein, the chip has main surface, back surface and multiple sides in between, wherein, the buffer glue is set on main and back surfaces with buffer glue Yang mode less between 1Mpa and 1Gpa to reduce heat stress force and to improve chip sealing structure reliability. This invention also provides one chip sealing process to form buffer glue to get best process final product rate.

Description

technical field [0001] The invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a chip packaging structure and a chip packaging process. Background technique [0002] In recent years, due to the rapid development of electronic technology and the rise of the semiconductor industry, electronic products that are more humane and better in function are constantly being introduced, and are designed towards the trend of light, thin, short and small. In the semiconductor industry, the purpose of chip packaging is to prevent the bare chip from being affected by moisture, heat and noise, and to provide electrical connection between the bare chip and external circuits, such as printed circuit boards (Printed Circuit Board, PCB) or other packaging substrates medium. [0003] Please refer to figure 1 , which represents a known chip packaging structure. The chip packaging structure 100 includes a chip 110, a substrate 120, and an encapsu...

AI Technical Summary

Problems solved by technology

Moreover, with the miniaturization of the chip packaging structure and the improvement of circuit integration, the above-mentioned thermal stress effect will become more obvious, which may cause serious warpage of the substrate and cause solder pads on the chip during the process. Problems such as damage, misalignment between chips and substrates, etc.

In more serious cases, it will cause the chip to be delaminated from the substrate and the package to be deformed (out of spec), which will affect the normal operation of the chip and the pass rate of the packaging process.

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