Dynamic storage management device and method

Abstract

The invention discloses a dynamic memory manage device and a relative method, relating to a device for distributing memory address and a relative method, which can resolve the problem of prior art that can not distribute memory address according to the instant flux of channel. The device comprises a data channel for sending out memory request, an available memory space resource pool for storing free memory address, a request processor for distributing free memory address, a memory operator for storing the memory data into a memory according to the memory address. And the dynamic memory manage method comprises that sending out storage request for the memory data, storing the free memory address in the memory, distributing memory address for the memory data from the free memory address, storing the memory data to the memory according to the distributed memory address. The invention directly distributes memory address to the memory data to distribute memory address according to the instant flux of the data channel, used to manage data storage in electric device.

Description

technical field [0001] The invention relates to a device and method for allocating storage addresses, in particular to a device and method for dynamically allocating storage addresses. Background technique [0002] Electronic devices generally use memories to cache various information and data, such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory). Electronic devices often need to handle the business of multiple data channels, so the memory must meet the storage requirements of multiple data channels at the same time, and the traffic characteristics of different data channels are different, resulting in very different requirements for storage capacity. Therefore, how to efficiently and flexibly allocate storage addresses in the memory to store data in multiple data channels is one of the main issues that need to be considered in the design process of electronic devices. As shown in FIG. 1 , each data channel sends storage data and a storage address...

AI Technical Summary

Problems solved by technology

Therefore, the above-mentioned static scheme has the following disadvantages: First, the efficiency is low. When the traffic between each data channel is uneven or the traffic of a certain data channel changes greatly, the storage addresses assigned to some data channels have been fully occupied, and the The storage addresses assigned to other data channels are still much richer, making RAM unable to be effectively used and reducing the utilization efficiency of RAM; second, the cost is high. In order to ensure that each data channel has sufficient storage capacity, it is necessary to increase each data channel. The storage capacity assigned to the channel, when there are many data channels, the total storage capacity of RAM is required to be large, resulting in high cost of producing electronic equipment

[0012] However, the semi-dynamic scheme needs to calculate the average traffic of each data channel, and allocate corresponding storage addresses for each data channel according to the average traffic. If the traffic of some data channels changes, the size of the storage capacity must be adjusted synchronously, and each It takes a long time to adjust. If the adjustment is too frequent, the amount of calculation will be increased and the work efficiency will be reduced.

[0013] Since the semi-dynamic scheme only allocates storage addresses according to the average traffic of the data channel, the average traffic of some data channels may be fixed, but the instantaneous traffic may vary greatly, and the data channel with a small average traffic may also have short-term bursts A large amount of data. In this case, the existing technical solutions cannot store the data of the data channel beyond the storage capacity allocated to the data channel, resulting in data loss, and the storage addresses allocated to other data channels may not be used. Causes waste of resources, making the utilization rate of memory lower

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