Chip package structure
A chip packaging structure and chip technology, applied in electrical components, electrical solid devices, circuits, etc., can solve problems such as long distances, false contacts, and short circuits, and achieve the effect of avoiding short circuits.
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[0041] Please refer to FIG. 2 , which is a schematic top view of a chip package structure according to a first embodiment of the present invention. The chip package structure 200 is a wire-bonded stacked chip package structure, which includes a substrate 210 , a first chip 220 and a second chip 230 on the first chip 220 . It should be noted that although the second chip 230 is arranged on the first chip 220, it is not located on the symmetrical center of the first chip 220, that is, the second chip 230 is not in the central area of the first chip 220, but in the first chip 220. A corner area of the chip 220. In this embodiment, the second chip 230 is located in the upper left corner area of the first chip 220, but in another embodiment (not shown), the second chip 230 can also be on one side of the first chip 220 Border area, its position can be adjusted appropriately.
[0042] In this embodiment, the first chip 220 sets the position and quantity of the first bonding p...
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