Semiconductor package and its chip bearing structure and production method
A bearing structure and semiconductor technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as poor electrical connection of chips
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no. 1 example
[0058] Referring to FIGS. 2A to 2G , they are schematic diagrams showing a first embodiment of the semiconductor package and its chip carrying structure and manufacturing method of the present invention.
[0059] First, as shown in FIGS. 2A and 2B , wherein FIG. 2B is a schematic cross-sectional view corresponding to FIG. 2A , which provides at least one substrate 21 and a carrier 23 with at least one opening 230 , so that the substrate 21 is placed in the carrier opening 230 , and the surface of the substrate 21 is provided with a component placement area 211 (as shown by a dotted line) and a coverage area 212, the component placement area 211 is set at the center of the substrate 21, for example, and the coverage area 212 is opposite to the component. surrounding area 211. In addition, a film (not shown) can be glued on the bottom of the carrier 23 to close one side of the opening 230 so that the substrate 21 can be placed thereon and accommodated in the opening 230 of the c...
no. 2 example
[0067] Referring to FIGS. 3A to 3D , they are schematic diagrams of a second embodiment of the semiconductor package and its chip carrying structure and manufacturing method of the present invention.
[0068] As shown in FIG. 3A, at least one substrate 31 and a carrier 33 with at least one opening 330 are provided, so that the substrate 31 is placed in the opening 330, and the surface of the substrate 31 is provided with a component receiving area 311 (as indicated by the dotted line). shown) and coverage area 312.
[0069] As shown in FIG. 3B , a patch 39 is first provided on the component receiving area 311 of the substrate 31 to cover the component receiving area 311, and packaging and molding operations are performed to accommodate the substrate 31. Part 33 is accommodated in the packaging mold 34, and the patch 39 is pressed against the top of the housing space of the packaging mold 34, so that when the housing space 340 of the packaging mold 34 is filled with packaging r...
no. 3 example
[0073] Referring to FIGS. 4A to 4C , they are schematic diagrams of a third embodiment of the semiconductor package and its chip carrying structure and manufacturing method of the present invention.
[0074] As shown in FIG. 4A , the substrate 41 is placed in the opening 430 of the carrier 43 by using the aforementioned method, and the encapsulation molding operation is performed, so that the encapsulant 45 is formed on the coverage area 412 of the substrate 41, and the substrate The encapsulant 45 is exposed from the component landing area 411 of 41 .
[0075] As shown in FIG. 4B , the semiconductor chip 42 is electrically connected to the component mounting area 411 of the substrate 41 through a plurality of conductive bumps 46 in a flip-chip manner, and is also placed on the component mounting area 411 of the substrate 41. The filling material such as the flip-chip underfill material 47 is formed so that the flip-chip underfill material 47 covers the conductive bump 46 and ...
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