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Method for forming isolation layer of semiconductor device

An isolation structure and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as complex processes

Inactive Publication Date: 2008-01-02
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, since a spacer removal process must be performed, the entire process becomes complicated

Method used

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  • Method for forming isolation layer of semiconductor device
  • Method for forming isolation layer of semiconductor device
  • Method for forming isolation layer of semiconductor device

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Embodiment Construction

[0020] 2A to 2G illustrate cross-sectional views showing a method for forming an isolation structure of a semiconductor device according to one embodiment of the present invention. In particular, FIGS. 2A to 2G illustrate a method for forming an isolation structure of a flash memory device.

[0021] Referring to FIG. 2A, a gate insulating layer 21, a polysilicon layer 22 for a gate electrode (floating gate), a buffer oxide layer 23, a pad layer 24, and an oxide layer 25 for a hard mask are sequentially formed on on the substrate 20. The gate insulating layer 21 includes an oxide-based material, and the pad layer 24 includes a nitride-based material. Hereinafter, the gate insulating layer 21 and the pad layer 24 are referred to as the gate oxide layer 21 and the pad nitride layer 24, respectively. The oxide layer 25 for a hard mask is etched using a predetermined photoresist pattern. A trench (not shown) is formed by etching the pad nitride layer 24, the buffer oxide layer 2...

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Abstract

A method for forming an isolation structure of a semiconductor device including a substrate where a gate insulating layer, a gate conductive layer, and a pad nitride layer are already formed includes etching the pad nitride layer, the gate conductive layer, the gate insulating layer and a portion of the substrate to form a trench, forming a wall oxide layer along an inner surface of the trench, forming a first insulating layer over a first resulting structure, including the wall oxide layer, to partially fill the trench, forming a second insulating layer using a spin coating method over a second resulting structure, including the first insulating layer, to fill the trench, polishing the first and second insulating layers using the pad nitride layer as a polish stop layer, removing the pad nitride layer, recessing the first and second insulating layers, and recessing the second insulating layer to a predetermined depth.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of Korean Patent Application No. 10-2006-0059597 filed on June 29, 2006, the contents of which are incorporated by reference in their entirety. Background technique [0003] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an isolation structure of a semiconductor device. [0004] With the development of semiconductor manufacturing technology, the line width of semiconductor devices decreases accordingly. In particular, the line width of the field region defined in the active region is reduced and thus the aspect ratio of the trench formed in the field region is increased. Therefore, the process of filling the trench to form the isolation structure becomes difficult. [0005] In order to improve the filling characteristics of the isolation structure, polysilazane (polysilazane, PSZ) high-density plasma ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
CPCH01L21/76224H01L21/18H01L21/76
Inventor 郭尚炫任洙贤
Owner SK HYNIX INC