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Memory controller

A control device and memory technology, applied in memory systems, instruments, memory address/allocation/relocation, etc., can solve problems such as inability to access SDRAM808 useless cycles, inability to store bank 1 output address, inability to access SDRAM, etc.

Inactive Publication Date: 2008-01-09
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At this time, the address cannot be output to bank 1 until the precharge operation on bank 1 is completed.
That is, useless cycles in which SDRAM808 cannot be accessed
[0011] Also, in the conventional memory control device 801, when a write access to write data into the SDRAM 808 is performed after a read access to read data from the SDRAM 808, a useless cycle in which the SDRAM cannot be accessed is generated according to the specification of the SDRAM 808.
Therefore, there is a problem that when a plurality of components 804, 805, 806, and 807 request read access and subsequently request write access, the number of cycles to access the SDRAM 808 increases compared with the time of continuous write access and continuous read access.
If a refresh operation is performed after writing access requests from multiple components 804, 805, 806, 807, useless cycles may sometimes occur according to the SDRAM808 specification

Method used

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Experimental program
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Embodiment approach 1

[0086] Next, embodiments of the first to eighth present inventions will be described with reference to FIGS. 1 , 2 , 8 and 9 . 4 is a block diagram of a memory control device according to Embodiment 1, FIG. 2 is a timing diagram of main signals in FIG. 1 , and FIG. 8 is a block diagram showing a coordination circuit according to Embodiment 1.

[0087] As shown in Figure 1, the components of this memory control device 105 include a coordinating circuit 101 for coordinating the memory access requests sent by multiple components 804, 805, and 806 for accessing the SDRAM 808, and a command generation block for generating memory commands to the SDRAM 808 102. Receive the storage address sent by the component that the coordination circuit 101 allows access to and output it to the address generation block 103 of the SDRAM 808, and write data sent by the component that the coordination circuit 101 allows access to Or the data latch block 104 that latches the data read from the SDRAM 8...

Embodiment approach 2

[0152] Next, embodiments of the ninth to fourteenth present inventions will be described with reference to FIGS. 1 , 3 , 10 and 11 . FIG. 3 is a main signal timing diagram of the second embodiment, FIG. 10 is a block diagram showing the coordination circuit 101 of the second embodiment, and FIG. 11 is a block diagram showing the data latch block 104 of the second embodiment.

[0153] The configuration of the memory control device 105 is the same as that of Embodiment 1 (FIG. 1), and the reference numerals in the figure are the same, and description thereof will be omitted.

[0154] As shown in FIG. 1 and FIG. 10 , the components of the coordinating circuit 101 include components that receive memory requests and storage addresses from the multiple components 804, 805, and 806 and judge that memory access is allowed at present according to the received storage addresses. Whether the second half memory bank and the first half memory bank of the next memory access request are to t...

Embodiment approach 3

[0186] Next, embodiments of the fifteenth to nineteenth inventions will be described with reference to FIG. 1 , FIG. 4 and FIG. 12 . FIG. 4 is a main signal timing diagram of Embodiment 3, and FIG. 12 is a block diagram showing a coordination circuit of Embodiment 3. As shown in FIG.

[0187] The configuration of the memory control device 105 is the same as that of Embodiment 1 (FIG. 1), and the reference numerals in the figure are the same, and description thereof will be omitted.

[0188] As shown in Fig. 1 and Fig. 12, the components of the coordinating circuit 101 include data units that receive memory requests from the multiple components 804, 805 and 806 and determine the requested memory access according to the received memory requests The data unit judging unit 1402 further instructs the request receiving block 1401 that generates a permission signal, the memory access priority specifying unit 1003 that specifies the priority of memory access from the plurality of comp...

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Abstract

There is provided a memory control device which prevents continuous access to the same bank of an SDRAM, thereby improving the processing time. The memory control device (105) controls a memory including a plurality of banks which can be accessed continuously by the bank division mode. The priority of the blocks (804, 805, 806) accessing the SDRAM (808) via the memory control device (105) is controlled in such a manner that memory access requests from these blocks continuously access different banks of the SDRAM (808).

Description

[0001] This application is a divisional application of the parent application with the title of invention "memory control device", the application date is January 26, 2004, and the application number is 200480001837.2 (PCT / JP2004 / 000671). technical field [0002] The present invention relates to a memory control device for controlling a memory composed of a plurality of memory banks in electronic equipment. Background technique [0003] In recent years, a synchronous dynamic random access memory (hereinafter abbreviated as SDRAM) capable of high-speed burst transfer of a cache memory frequently used in personal computers in synchronization with a clock has been used. This SDRAM can switch the sequential access mode and the random access mode of the bank division mode. In the bank division mode, as four memory areas, there are: bank 0 whose 2-bit bank signal is "00", bank 1 which is "01", bank 2 which is "10", and which is "11" storage bank 3. While switching the memory ban...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/06G06F12/00G06F13/16
CPCG06F12/0607G06F13/161G06F13/1647G06F12/00
Inventor 秋月麻水子青木透上田泰志
Owner PANASONIC CORP
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