Dual gate CMOS semiconductor device and method for manufacturing the same

Abstract

A dual gate Complementary Metal Oxide Semiconductor (CMOS) device includes a gate electrode of PMOS transistor implanted with germanium and indium ions and formed on a gate insulating film; a gate electrode of NMOS transistor not implanted with germanium and indium ions and formed on the gate insulating film; a source / drain region formed in a substrate exposed at both sides of the gate electrodes of the PMOS and NMOS transistors; and metal silicides formed on the source / drain region and the gate electrodes. A method for manufacturing a dual gate CMOS device, the method includes forming a gate insulating film; forming a polycrystalline silicon layer; forming an ion implantation mask; implanting germanium (Ge) and indium (In) ions into a PMOS transistor region of the substrate; and removing the ion implantation mask, patterning the polycrystalline silicon layer, and forming gate electrodes for PMOS and NMOS transistors.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2006-0083833 (filing date: August 31, 2006), the entire contents of which are incorporated herein by reference. technical field [0002] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a semiconductor device including ion implantation and a manufacturing method thereof. Background technique [0003] Various aspects of semiconductor manufacturing technology have focused on increasing the integration level of semiconductor devices (eg, enabling smaller scale devices). As the integration level increases, the ion implantation process plays an important role in realizing the low electric field of the channel / junction region due to the characteristics of semiconductor devices. In particular, the ion implantation process should allow high doses to be applied and still produce shallow junction properties. [0004] In some semiconductor manufacturing pro...

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Problems solved by technology

[0009] However, the method using polysilicon-germanium has the disadvantage that an additional epitaxial process is required, which increases the complexity of implementing the method

The method using the gate oxynitride film has a defect that the nitrogen concentration increases, which reduces the mobility of the NMOS transistor, thereby degrading its performance

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