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Semi-duplex serial port communication system and method using UART

A transceiver, universal asynchronous technology, applied in the direction of duplex signal operation, data exchange through path configuration, program control in sequence/logic controller, etc., can solve the waste of 485 communication resources and CPU resources, reduce 485 bandwidth Utilization, aggravating CPU workload and other issues, to achieve the effect of saving 485 communication resources, improving 485 bandwidth utilization, and improving communication efficiency

Inactive Publication Date: 2010-05-12
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, due to the high or low communication rate, the communication object may be fast or slow from receiving a message to giving a response. As a result, the current processing for this period of time is a fixed long time delay before releasing the 485 bus to ensure a high communication rate. In the low case, the bus can also be released after sending the response message, but in the case of a high communication rate, the bus must be idle, and other communication objects using the same bus have been waiting to obtain bus resources, which greatly improves Wasted 485 communication resources and CPU resources, increased CPU workload, reduced CPU processing capacity, and reduced 485 bandwidth utilization

Method used

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  • Semi-duplex serial port communication system and method using UART
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  • Semi-duplex serial port communication system and method using UART

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Embodiment Construction

[0032] like figure 1 As shown, the communication party A communicates with the half-duplex communication object B. The communication party A is composed of a CPU with a timer, a universal asynchronous transceiver (UART), an EPLD register, and a half-duplex 485 driver chip. Among them, the EPLD register or the FPGA device is a control signal device, and the EPLD register is optional. If there is no EPLD, the signal resources of the CPU itself can be used. Of course, the EPLD register can also be replaced by FPGA and other devices that can provide control signals.

[0033] Communicating parties A and B communicate through the 485 bus.

[0034] The communication object B handles the listening state at ordinary times. When the sender A needs to send a message to B, the CPU sends a message to the 485 driver chip through the TX of the UART, and sets the TX enable signal through the hardware logic EPLD to enable the half-duplex 485 driver chip. The send bus, and then the sent data ...

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Abstract

The half duplex serial comm (HDSC) system includes Universal Asynchronous Receiver Transmitter (UART) and half duplex driven chip (HDDC) as well as CPU with timer. Through TX of UART, CPU sends message to HDDC. The CPU does following things: sending TX enable signal to HDDC, making HDDC send data to bus; when empty interrupt of the transmission buffer in UART is generated, CPU enables timer so that the timer generates interrupt after delay; shutting down the timer in the interrupt, and shutting down TX enable signal; enabling RX enable signal and releasing bus. The invention also discloses HDSC method of using UART. The invention guarantees that 485 bus is released when data just are sent out completely so as to raise comm efficiency between embedded type comm devices of using UART.

Description

technical field [0001] The invention relates to a UART (Universal Asynchronous Transceiver) communication technology, in particular to a half-duplex serial communication system and a communication method using the UART. Background technique [0002] In the half-duplex communication device, the communication between UART and the communication object is carried out through the half-duplex 485 driver chip. When it is necessary to send a message to the communication object, the CPU usually sets the TX enable (send enable) signal to enable the UART to send data to the half-duplex 485 driver chip, and then the CPU can send a message to the communication object through the UART, and the communication object receives A reply is given after the message according to the corresponding protocol. [0003] However, due to the high or low communication rate, the communication object may be fast or slow from receiving a message to giving a response. As a result, the current processing for ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L5/16G06F13/42H04L12/40G05B19/05
Inventor 张爱卿
Owner ZTE CORP