Semi-duplex serial port communication system and method using UART
A transceiver, universal asynchronous technology, applied in the direction of duplex signal operation, data exchange through path configuration, program control in sequence/logic controller, etc., can solve the waste of 485 communication resources and CPU resources, reduce 485 bandwidth Utilization, aggravating CPU workload and other issues, to achieve the effect of saving 485 communication resources, improving 485 bandwidth utilization, and improving communication efficiency
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[0032] like figure 1 As shown, the communication party A communicates with the half-duplex communication object B. The communication party A is composed of a CPU with a timer, a universal asynchronous transceiver (UART), an EPLD register, and a half-duplex 485 driver chip. Among them, the EPLD register or the FPGA device is a control signal device, and the EPLD register is optional. If there is no EPLD, the signal resources of the CPU itself can be used. Of course, the EPLD register can also be replaced by FPGA and other devices that can provide control signals.
[0033] Communicating parties A and B communicate through the 485 bus.
[0034] The communication object B handles the listening state at ordinary times. When the sender A needs to send a message to B, the CPU sends a message to the 485 driver chip through the TX of the UART, and sets the TX enable signal through the hardware logic EPLD to enable the half-duplex 485 driver chip. The send bus, and then the sent data ...
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