Semiconductor device

Abstract

In a J-FET for large current use, there has been a limitation on reduction in a chip size or enlargement of the operation regions because two operation regions are arranged in line along a diagonal line of a chip. To eliminate the limitation, in this invention, gate regions are extended in a direction along one of sides of a chip, two operation regions are arranged along a first diagonal line of the chip, and two pad electrodes are arranged along a second diagonal line of the chip. Thus, the area on the chip can be effectively utilized. As a result, a chip size can be reduced with the same operation region area, and the operation region area can be increased with the same chip size.

Description

technical field [0001] The present invention relates to a semiconductor device used in a high-frequency device, and in particular, to a semiconductor device in which a chip size is reduced and high-frequency characteristics are improved. Background technique [0002] 6 and 7 are diagrams showing examples of junction FETs (hereinafter referred to as J-FETs) used in high-frequency devices. [0003] FIG. 6 is a plan view showing J-FET 200 . Referring to Fig. 6 (A), in J-FET200, on the semiconductor substrate 20 that constitutes semiconductor chip, dispose the first operation region 35a and the second operation region 35b, and the first pad electrode 29p and the second pad electrode 29p connected with them respectively. Pad electrode 30p. [0004] Since the first operation region 35a and the second operation region 35b have the same configuration, the first operation region 35a will be described below. [0005] FIG. 7 is a diagram showing an example of a conventional J-FET, a...

AI Technical Summary

Problems solved by technology

However, in conventional designs, there is a limit to miniaturizing the chip size while maintaining the desired current capacity

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