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Method for protecting an alignment mark

A technology for aligning marks and oxide films, which is applied in the direction of photolithography, instruments, electrical components, etc. on the pattern surface, and can solve the problem of not being able to sense the alignment marks

Inactive Publication Date: 2010-12-08
DONGBU HITEK CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if the alignment mark has a step height less than the minimum step height due to dishing and / or erosion in the CMP process, the alignment mark may not be sensed

Method used

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  • Method for protecting an alignment mark
  • Method for protecting an alignment mark
  • Method for protecting an alignment mark

Examples

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Embodiment Construction

[0015] Figure 2A to Figure 2D A process for protecting alignment marks when forming via contacts according to an embodiment of the present invention is illustrated. Such as Figure 2A As shown, a dielectric layer 202 (eg, borophosphosilicate glass (BPSG)) is formed on and / or over a semiconductor substrate 200 in accordance with an embodiment of the invention. Dielectric layer 202 may be used to form via contacts. The semiconductor substrate 200 may include an alignment mark 200a. The alignment mark 200a may include a capping oxide film (SiH 4 ) and / or pre-metal dielectric (PMD). A CMP process may be performed to planarize the dielectric layer 202 .

[0016] Such as Figure 2B As shown, a cap oxide film 204 (eg, SiH 4 ). In this embodiment, capping oxide film 204 may have a conventional thickness 204b and an additional thickness 204a. The normal thickness 204b may be the nominal thickness capping oxygen that is conventionally deposited when forming capping oxide films...

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Abstract

The invention discloses a method for protecting an alignment mark on a semiconductor substrate, which includes forming a dielectric layer on the semiconductor substrate having the alignment mark, forming a cap oxide film on the dielectric layer, wherein the cap oxide film is formed to have a regular thickness and an additional thickness, etching a portion of the dielectric layer and the cap oxidefilm to expose the semiconductor substrate to thereby form a via hole, filling the via hole with a metal, and performing a chemical mechanical polishing process with the metal and the cap oxide film to form a via contact.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2006-0083917 (filing date: August 31, 2006), the entire contents of which are incorporated herein by reference. technical field [0002] The present invention contemplates a method for protecting the alignment marks, in particular a method capable of minimizing the loss of the alignment marks after a chemical mechanical polishing process. Background technique [0003] Among relatively highly integrated semiconductor devices, planarization processes such as chemical mechanical polishing (CMP) are important in ultra large scale integration (ULSI). Therefore, alignment techniques with relatively high reliability acting on planarized wafers are important in microlithography. [0004] Such as figure 1 As shown, in order to be sensed in the photolithography process, the alignment mark needs to satisfy the minimum width (X) and the minimum step height (Y). However, if the alignment mark has a step heigh...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/00H01L23/544
CPCG03F9/708H01L21/76829H01L23/544G03F9/7084H01L2223/54453H01L2924/0002H01L2924/00G03F7/70983H01L21/30625
Inventor 沈相旼
Owner DONGBU HITEK CO LTD