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Stacked multi-chip semiconductor package structure and package method

A technology of packaging structure and packaging method, which is applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc. Enhanced and improved flexibility

Inactive Publication Date: 2008-05-21
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] The problem to be solved by the present invention is to provide a stacked multi-chip semiconductor packaging manufacturing method to prevent the flexibility of semiconductor packaging due to the single use of wire bonding or flip-chip bonding, which cannot meet the needs of various applications. need

Method used

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  • Stacked multi-chip semiconductor package structure and package method
  • Stacked multi-chip semiconductor package structure and package method
  • Stacked multi-chip semiconductor package structure and package method

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Embodiment Construction

[0032] With the increasing demand for miniaturization, light weight and multi-functionalization of electronic components, the density of semiconductor packaging is increasing. At present, the stacked multi-chip semiconductor packaging method reduces the packaging area and improves the density and function. Due to the single use of wire bonding or flip-chip bonding for connection, the flexibility of semiconductor packaging is not high, and it cannot meet the needs of various applications. The present invention improves the flexibility of semiconductor packaging by changing the connection structure of stacked multi-chip semiconductor packaging and using the connection technology of metal wire bonding and flip-chip bonding to meet the needs of various applications; in addition, due to The use of flip-chip bonding connection technology reduces the number of metal bonding wire connections and enhances the electrical performance of the packaging system. In order to make the above ob...

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Abstract

The invention discloses a packing structure of heap type multi-chip semiconductor, which comprises at least an inverted chip, at least a forward erected chip and a lead frame; wherein, the inverted chip is electrically connected with the lead frame; the forward erected chip is electrically connected with the lead frame; the inverted chip is arranged on the lead frame and the forward erected chip is bound on the inverted chip. Due to adopting the heap type multi-chip semiconductor packing structure and by using the connecting technology of mixing metal wire bonding and the inverted chip bonding, the invention has the advantages of improving the flexibility of the semiconductor and meeting requirements of each application; meanwhile, connecting times of metal bonding wire is decreased due to adopting the connecting technology of the inverted chip bonding and the electrical performance of the packing system is enhanced.

Description

technical field [0001] The invention relates to a stacked multi-chip semiconductor packaging structure and packaging method, in particular to a semiconductor packaging structure and packaging method in which a plurality of front-mounted chips and a plurality of flip-chips are connected to each other through bonding wires, solder bumps and lead frames. Background technique [0002] As the demand for miniaturization, light weight and multi-functionalization of electronic components increases day by day, the packaging density of semiconductors increases continuously. Therefore, it is necessary to reduce the size of the package and the area occupied by the package. Among the technologies developed to meet the above requirements, the multi-chip semiconductor packaging technology plays an indicative role in the overall cost, performance and reliability of packaged chips. [0003] However, in the multi-chip semiconductor packaging process, the connection method between chips also h...

Claims

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Application Information

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IPC IPC(8): H01L25/00H01L23/488H01L21/50H01L21/60
CPCH01L2224/32145H01L2224/48091H01L2224/73265H01L2224/49175H01L2224/32245H01L2224/16H01L2224/48247H01L2924/181H01L2224/05553H01L2224/05554H01L2224/16245H01L2224/73253H01L2924/00014H01L2924/00H01L2924/00012
Inventor 王津洲
Owner SEMICON MFG INT (SHANGHAI) CORP
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