Technique for reducing silicide non-uniformities by adapting a vertical dopant profile

Abstract

By modifying the vertical dopant concentration in deep drain and source regions, the reaction behavior during the formation of metal silicide regions may be controlled. For this purpose, an increased dopant concentration is formed around a target depth for the metal silicide interface, thereby reducing the reaction speeds and thus improving the uniformity of the resulting metal silicide interface.

Description

technical field [0001] The present invention relates generally to the field of fabrication of integrated circuits, and more particularly to semiconductor devices having metal silicide portions on semiconductor regions to reduce the electrical resistance of said semiconductor regions. Background technique [0002] In modern ultra-high density integrated circuits, device features are steadily decreasing to enhance device performance and functionality. However, reducing feature size can cause problems that may partially negate the benefits gained through feature size reduction. In general, reducing the feature size of, for example, a transistor component results in a decrease in the channel resistance of the transistor component, resulting in a higher drive current capability and increased switching speed of the transistor. However, in reducing the feature size of these transistor devices, the resistance of the wires and contact regions (i.e., the regions connecting transistor...

AI Technical Summary

Problems solved by technology

Furthermore, as the drive to scale down semiconductor devices continues, the non-uniformity of the metal silicide region 117 may have a negative impact on the performance of next generation devices with tighter process tolerance settings

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