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Thin film type semiconductor packaging construction for increasing corner pin joint intensity

A bonding strength, thin-film technology, applied in semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc., can solve the problems of general products without structure, bump 121 breakage, pin 112 high stress, etc.

Inactive Publication Date: 2008-07-30
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the actual packaged product, the pins 112 located on both sides will suffer from large stress, which is a stress concentration area, causing the bump 121 bonded to it to break
[0004] It can be seen that the above-mentioned existing thin-film semiconductor packaging structure obviously still has inconvenience and defects in structure and use, and needs to be further improved urgently.
In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and the general products do not have a suitable structure to solve the above-mentioned problems. This is obviously related. The problem that the industry is eager to solve

Method used

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  • Thin film type semiconductor packaging construction for increasing corner pin joint intensity
  • Thin film type semiconductor packaging construction for increasing corner pin joint intensity
  • Thin film type semiconductor packaging construction for increasing corner pin joint intensity

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Embodiment Construction

[0044] In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the following is a specific implementation of the thin-film semiconductor package structure proposed in accordance with the present invention to enhance the bonding strength of corner pins with reference to the accompanying drawings and preferred embodiments. The method, structure, characteristics and effects are described in detail later.

[0045] image 3 , Figure 4 and Figure 5 It is related to a thin-film semiconductor package structure disclosed in the first embodiment of the present invention that enhances the bonding strength of corner pins.

[0046] See image 3 and Figure 4 As shown, a thin-film semiconductor package structure 200 for enhancing the bonding strength of corner pins mainly includes a substrate 210, a chip 220, and a sealant 230. The substrate 210 has a flexible dielectric layer 211, a plurality of pins 212, and at l...

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Abstract

The invention relates to a thin-film semiconductor package structure for enhancing lead bonding strength at corners, which mainly comprises a substrate, a chip provided with a plurality of bumps and a sealant for sealing the bumps. The substrate includes a flexible dielectric layer, a plurality of pins and at least one dummy pin, wherein the flexible dielectric layer is provided with a chip bonding land; the pins and the dummy pins are attached on the flexible dielectric layer and extended to the chip bonding land; and the dummy pins are positioned at corners of the chip bonding land. The dummy pins can enhance the bonding strength at corners to prevent the pins from fracturing due to the stress.

Description

Technical field [0001] The present invention relates to a thin-film semiconductor packaging structure, in particular to a thin-film semiconductor packaging structure that strengthens the bonding strength of corner pins. Background technique [0002] Thin-film semiconductor packaging structures have the advantages of being ultra-thin and light-weight, such as tape carrier package (TCP) and chip-on-film package (COF). However, the thermal expansion coefficient of the substrate used as a wafer carrier is still different from that of semiconductor wafers, resulting in internal stress during thermal cycle tests or actual calculations, and the leads are easily broken or poorly joined where the stress may be concentrated. [0003] See figure 1 and figure 2 As shown, a conventional thin-film semiconductor packaging structure 100 includes a substrate 110, a chip 120, and an encapsulant 130. The substrate 110 has a flexible dielectric layer 111 and a plurality of pins 112. The flexible d...

Claims

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Application Information

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IPC IPC(8): H01L23/498H01L23/31
CPCH01L2224/50
Inventor 沈弘哲沈更新
Owner CHIPMOS TECH INC