Multi-chip stacking structure and its making method

Abstract

A multi-chip stacking structure and a preparation method thereof provide a chip bearing weight part and a plurality of chips. The surface edges of the chips are provided with a plurality of welding pads, a first chipset is formed through making the chips stack on the bearing weight part with ladder shaped mode towards the direction deviating the lower welding pads, the welding pads are protruded, the first chipset and the chip bearing weight part are electrically connected through a plurality of first bonding wires; another chip is connected with the first chipset through an adhesion layer, wherein the adhesion layer is provided with a plurality of fillers to support the chip or uses an adhesion film to coat the first bonding wires part arranged between the chip and the topmost chips of the first chipset, a second chipset is formed through making the other chips stack with the ladder shaped mode, the welding pads are protruded, and then the second chipset and the chip bearing weight part are electrically connected through a plurality of second bonding wires, thus a plurality of chips are stacked without the principle extra increasing areas and heights of encapsulation parts, applicable to light, thin and small electric devices.

Description

technical field [0001] The invention relates to a semiconductor structure and its manufacturing method, in particular to a multi-chip stacking structure and its manufacturing method. Background technique [0002] Due to the miniaturization of electronic products and the increase in the demand for high operating speeds, in order to improve the performance and capacity of a single semiconductor package structure to meet the needs of miniaturization of electronic products, the semiconductor package structure has become a trend of multi-chip modularization (Multichip Module) , so that two or more semiconductor chips are combined in a single package structure, so as to reduce the volume of the overall circuit structure of electronic products and improve electrical functions. That is, the multi-chip package structure can minimize the limitation of the operating speed of the system by combining two or more chips in a single package structure. In addition, the multi-chip package st...

AI Technical Summary

Problems solved by technology

[0007] However, there are still some problems in the aforementioned multi-chip stacking structure. First, due to the need to additionally add a buffer sheet during the chip stacking process, the manufacturing cost and steps are increased; The height of the multi-chip stack structure cannot be effectively reduced, which is not conducive to the manufacture of thin electronic devices (such as Micro-SD cards)

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