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Method and device for controlling a memory access in a computer system with at least two execution units

A computer system, a technology for controlling memory, applied in memory systems, memory architecture access/allocation, calculation, etc., and can solve problems such as incorrect calculation results

Inactive Publication Date: 2008-08-06
ROBERT BOSCH GMBH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The result may be an incorrect calculation

Method used

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  • Method and device for controlling a memory access in a computer system with at least two execution units
  • Method and device for controlling a memory access in a computer system with at least two execution units
  • Method and device for controlling a memory access in a computer system with at least two execution units

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Embodiment Construction

[0033] In the following, an execution unit may mean not only a processor / core / CPU, but also an FPU (Floating Point Unit), a DSP (Digital Signal Processor), a coprocessor, or an ALU (Arithmetic Logical Unit (arithmetic logic unit) unit)).

[0034] Thus, in some multiprocessor systems, caches are used only to avoid contentions on the system bus and / or the memory bus. If there is only one execution unit, caching is not necessary in this case, since the memory is fast enough to service the read requests of one execution unit.

[0035]FIG. 1 shows a first embodiment of a multiprocessor system C100 with two execution units C110 a and C110 b , which can access a memory via a bus C10 . Unit C130 regulates how the bus C10 is accessed according to the mode of the system C100. In performance mode, switch C131 is closed and switch C132 is opened. Execution unit C110b therefore accesses bus C10 via cache C120 and bus connection unit C150. Execution unit C110 a is directly connected to ...

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Abstract

The invention relates to a method and device for controlling a memory access in a computer system with at least two execution units. An intermediate memory, particularly a cache, is provided as well as switching means and comparison means are provided. A performance mode and a comparison mode are switched between. The invention is characterized in that during the comparison mode, the intermediate memory is accessed by both execution units and only one execution unit is access during the performance mode.

Description

technical field [0001] The invention proceeds from a method and a device for comparing output data of at least two execution units of a microprocessor according to the preambles of the independent claims. Background technique [0002] Transient errors caused by alpha particles or cosmic radiation are increasingly becoming a problem for integrated circuits. Due to reduced structure widths, reduced voltages and higher clock frequencies, the probability increases that voltage peaks caused by alpha particles or cosmic radiation will distort logic values ​​in integrated circuits. The result may be an erroneous calculation. Such errors must therefore be reliably detected in safety-relevant systems. [0003] In safety-related systems, such as ABS control systems in motor vehicles, which have to reliably detect malfunctions of electronic devices, it is in the corresponding control devices of such systems that redundancy is usually provided for error detection. Thus, for example, ...

Claims

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Application Information

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IPC IPC(8): G06F11/16G06F12/08G06F12/084
CPCG06F11/1641G06F11/165G06F12/084G06F2212/601G06F2201/845
Inventor R·韦伯尔B·米勒E·博尔Y·科拉尼R·格默利克
Owner ROBERT BOSCH GMBH