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Mask territory verification method in semiconductor fabrication process

A verification method and manufacturing process technology, which is applied to the photolithographic process of the pattern surface, the photolithographic process exposure device, the original for photomechanical processing, etc., can solve the problem of high cost and the inability to verify whether the old and new masks have the same layout, machine failure and other issues, to achieve the effect of cost saving

Inactive Publication Date: 2008-08-27
GRACE SEMICON MFG CORP
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Problems solved by technology

[0003] In semiconductor manufacturing, wafers undergo multiple processing steps sequentially during the manufacturing process. Masks are used during the wafer exposure process. However, masks may be damaged due to various reasons, such as human error. operation, machine failure, or severe reticle defect, so that a new mask needs to be made
In the traditional mask making process, the quality inspection of the new mask needs to refer to the pass rate data of the test piece of the semiconductor wafer, and the period of waiting for the pass rate data of the test piece will take at least one month. A large number of procedures must wait until the results of the pass rate of the test piece come out before continuing, which wastes a lot of time and the cost of conducting the pass rate test of the test piece is also relatively high
[0004] In the semiconductor mask manufacturing process, some abnormal patterns may be formed on the mask, and these abnormal patterns will be transferred to the wafer to form defects in the subsequent exposure process, so the mask defect detection tool appears, but This type of mask defect detection tool cannot be used to verify that old and new masks have the same layout

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  • Mask territory verification method in semiconductor fabrication process
  • Mask territory verification method in semiconductor fabrication process
  • Mask territory verification method in semiconductor fabrication process

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Embodiment Construction

[0018] In order to better understand the technical content of the present invention, preferred specific embodiments are given together with the attached drawings for description as follows.

[0019] figure 1 For a flowchart of a mask layout verification method according to a preferred embodiment of the present invention, please refer to figure 1 , the mask layout verification method of the present invention, the process includes step 100: respectively using the first mask and the second mask to expose a wafer to obtain a wafer exposure map, according to a preferred embodiment of the present invention, The above-mentioned wafer exposure map is synthesized from two mask exposure maps obtained by exposing the above-mentioned wafer by using the above-mentioned first mask and the above-mentioned second mask respectively, wherein the above-mentioned wafer exposure map includes a plurality of first The mask lattice and the plurality of second mask lattices, the above-mentioned wafer...

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Abstract

The invention provides a mask verification method in the semiconductor manufacturing technology. The invention comprises the following steps that: a wafer is exposed by utilization of a first mask and a second mask, and a wafer exposure image is obtained; defect scanning of the wafer exposure image is performed, and a wafer detect scanning image is obtained; judgment is made whether the first mask and the second mask are consistent according to the wafer detect scanning image. Whether the novel mask and the prior mask are consistent can be visually and accurately determined through the mask verification method; qualification rate data of reference test pieces is not needed, thereby the test piece waiting period is not needed; simultaneously, the cost for a qualification rate experiment of the test pieces is saved.

Description

technical field [0001] The invention relates to a layout verification method in a semiconductor manufacturing process, and in particular to a mask layout verification method. Background technique [0002] With the rapid development of modern science and technology today, the semiconductor industry has become an indispensable part. Semiconductor materials are widely used in various high-tech equipment. For example, in the field of integrated circuit manufacturing, the manufacture of semiconductor wafers is very important. important. [0003] In semiconductor manufacturing, wafers undergo multiple processing steps sequentially during the manufacturing process. Masks are used during the wafer exposure process. However, masks may be damaged due to various reasons, such as human error. operation, machine failure, or a severe reticle defect that necessitates making a new mask. In the traditional mask making process, the quality inspection of the new mask needs to refer to the pa...

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Application Information

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IPC IPC(8): G03F1/00G03F7/20G03F1/72
Inventor 李杰
Owner GRACE SEMICON MFG CORP