Mask territory verification method in semiconductor fabrication process
A verification method and manufacturing process technology, which is applied to the photolithographic process of the pattern surface, the photolithographic process exposure device, the original for photomechanical processing, etc., can solve the problem of high cost and the inability to verify whether the old and new masks have the same layout, machine failure and other issues, to achieve the effect of cost saving
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[0018] In order to better understand the technical content of the present invention, preferred specific embodiments are given together with the attached drawings for description as follows.
[0019] figure 1 For a flowchart of a mask layout verification method according to a preferred embodiment of the present invention, please refer to figure 1 , the mask layout verification method of the present invention, the process includes step 100: respectively using the first mask and the second mask to expose a wafer to obtain a wafer exposure map, according to a preferred embodiment of the present invention, The above-mentioned wafer exposure map is synthesized from two mask exposure maps obtained by exposing the above-mentioned wafer by using the above-mentioned first mask and the above-mentioned second mask respectively, wherein the above-mentioned wafer exposure map includes a plurality of first The mask lattice and the plurality of second mask lattices, the above-mentioned wafer...
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