Flash memory address translation layer system

Abstract

A flash memory address translation layer system connected with a flash memory and an EMS read / write controller comprises: an instruction buffer for connecting with the EMS memory read / wrote controller; a logical address buffer for connecting the EMS memory read / wrote controller; a data buffer for connecting with the EMS memory and the EMS memory read / wrote controller; a pair of assistant controller for providing an instruction assistant function for controlling data's read / write; a microprocessor for connecting the instruction buffer and two assistant controllers; an address translation unit for connecting the microprocessor; a flash memory address buffer for connecting with the assistant controller, address translation unit and the flash; a adjustable address translation layer unit for connecting with an assistant controller; a quick fetch instruction and data buffer for connecting with the adjustable address translation unit. The invention can greatly reduce the number of invalid data collection and occupy capacity of the flash memory, and has a quick mechanism with space efficiency to improve and quicken the efficiency which the logical address corresponds to the real flash address.

Description

technical field [0001] The present invention relates to one, in particular to a flash memory address translation layer system. Background technique [0002] Flash memory is widely used in computer hosts or consumer electronics products, such as flash memory in existing flash drives and MP3 players, which are the most common examples of flash memory applications. However, NAND flash memory (NAND flash memory) is currently widely used For embedded storage systems, flash memory is composed of many pages (Page), each page size is fixed (for example, 512 bytes), and some consecutive pages (for example, 32 pages) can form a block (Block) , due to the characteristics of flash memory, it is not allowed to write to the same page in the same block, unless there is an action to erase the block where the page is located in advance, due to this access feature, it also causes problems in managing flash memory difficulties. [0003] Usually, in order to allow flash memory to operate unde...

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Problems solved by technology

[0008] In the above-mentioned existing flash memory address translation layer system, when the flash memory capacity is getting larger and larger, the flash memory address translation layer maintains its address translation table in order to save random access memory space, and adopts a block-level corresponding mechanism, but this area The block-level correspondence mechanism will cause inefficiency in the process of "corresponding the logical address to the real address of the flash memory", because the flash memory is read and written in pages as the unit of reading, but at the block level in order to obtain the latest page address Sometimes it may take a while to search for a page in a block, which affects the efficiency and speed of the flash read and write

[0009] In addition, in terms of relevant prior patent documents, such as China Taiwan Patent Announcement No. 1253564 "Flash Memory Data Access Management System and Its Method" invention patent case and No. 1249670 "Data can be sequentially written into the flash memory System and its method” invention patent case respectively reveals the typical existing flash memory data read and write redirection technology, the management method of good and bad blocks, and the method and technology of sequentially writing data in virtual blocks into flash memory. In terms of reading and writing and forwarding, it is also necessary for the logical address to correspond to the address of the real flash memory." The process is inefficient, and the speed of data reading and writing is also adversely affected

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