Finite impulse response digit filter capable of configuring parameter

A digital filter and configuration parameter technology, applied in the direction of digital technology network, impedance network, electrical components, etc., can solve the problems of occupying system resources, dynamically adjusting the filter coefficient of the filter, single characteristic filtering work, etc.

Inactive Publication Date: 2008-09-03
HARBIN UNIV OF SCI & TECH
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Problems solved by technology

Among them, the digital filter implemented by computer program can easily adjust the filtering characteristics, but the amount of data calculation is large, which takes up system resources.
The FIR filter implemented by DSP device is relatively simple and widely used. The disadvantage is that the program is executed sequentially. Although the performance of DSP device is continuously improved, it is still limited in some occasions with high real-time requirements; FPGA device is a hardware parallel structure. , so the parallel

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  • Finite impulse response digit filter capable of configuring parameter
  • Finite impulse response digit filter capable of configuring parameter
  • Finite impulse response digit filter capable of configuring parameter

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Embodiment Construction

[0048] The overall structure of the data filtering system is as follows: Figure 27 shown. A 10-bit A / D converter is used to perform analog-to-digital conversion on the signal, and the digital signal is input to the FPGA device, where FIR filtering is performed in the FPGA device, and the filtered data is transmitted to the host computer through the USB2.0 bus. On the other hand, the host computer downloads the calculated configuration parameters to the FPGA through the USB2.0 bus to realize FIR filters with different windows and different cut-off frequencies.

[0049] 1. FPGA-based digital filter design

[0050] The overall structure of the FPGA chip is as follows Figure 28 shown. The system selects the working state according to the instruction of the upper computer, and performs state jump under the control of the state machine. In the state of filter parameter configuration, the host computer inputs the configuration parameters into the parameter FIFO for buffering thr...

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Abstract

The invention discloses a finite impulse response digit filter based on FPGA which can use computer to dynamic configure filtering parameters. The invention uses 10 bit A/D converter to execute A/D conversion, digit signals are input into the FPGA device, FIR filtering is carried out in the FPGA device, and the filtered data are transferred to an upper machine through USB2.0 bus. On the other hand, the upper machine transfers the configure parameters obtained by calculation to the FPGA device through USB2.0 bus, so as to realize the FIR filter with different windows and different cutoff frequency. A lower machine taking the FPGA as the kernel device can fulfill heavy data filtering work, alleviates the problem of the upper machine, and can satisfy the high-speed real-time requirement of the system; and because the upper machine can configure the key parameters of the operational procedure in the FPGA through the USB2.0 bus, the flexibility requirement of the system can be satisfied.

Description

technical field [0001] The invention relates to a digital filter, specifically a finite impulse response digital filter with configurable parameters. technical background [0002] At present, the FIR digital filter can be implemented by software, such as a computer program; or by hardware, such as DSP or FPGA. Among them, the digital filter implemented by computer program can easily adjust the filter characteristics, but the amount of data calculation is large, which takes up system resources. The FIR filter implemented by DSP device is relatively simple and widely used. The disadvantage is that the program is executed sequentially. Although the performance of DSP device is continuously improved, it is still limited in some occasions with high real-time requirements; FPGA device is a hardware parallel structure. , so the parallel iterative algorithm of the digital filter is very suitable to be realized by FPGA, but the common problem is that the filter coefficient of the fi...

Claims

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Application Information

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IPC IPC(8): H03H17/02
Inventor 赵洪刘艳于效宇丁倩岳振
Owner HARBIN UNIV OF SCI & TECH
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