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FET devices and its manufacture method

一种场效应晶体管、晶体管的技术,应用在晶体管、半导体/固态器件制造、半导体器件等方向,能够解决复杂性、应力沟道技术不是令人十分满意、无效性等问题

Inactive Publication Date: 2008-09-10
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, all techniques used to date to obtain the above-mentioned stress channels are not fully satisfactory, either because of their complexity, or because of their relative inefficiency

Method used

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  • FET devices and its manufacture method
  • FET devices and its manufacture method
  • FET devices and its manufacture method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0010] It will be appreciated that field effect transistors (FETs) are well known in the field of electronics. The standard components of a FET are a source, a drain, a body between the source and drain, and a gate. The gate capping body also enables the introduction of a conductive channel into the body between the source and drain. In common terms, the channel is occupied by the bulk. Typically, the gate is separated from the body by a gate insulator. Whether a FET evolves into an NFET or a PFET depends on whether the "on-state" current in the channel is carried by electrons or holes. (In different terminology, NFET and PFET devices are often referred to as NMOS and PMOS devices.) It is also understood that NFET and PFET devices are often used together in circuits, usually coupled into a CMOS structure. The fabrication of NFETs, PFETs and CMOS is well established in this field. It can be appreciated that a large number of steps are involved in the above process, and each...

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PUM

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Abstract

NFET and PFET devices with separately stressed channel regions, and methods of their fabrication is disclosed. A FET is disclosed which includes a gate, which gate includes a metal in a first state of stress. The FET also includes a channel region hosted in a single crystal Si based material, which channel region is overlaid by the gate and is in a second state of stress. The second state of stress of the channel region is of an opposite sign than the first state of stress of the metal included in the gate. The NFET channel is usually in a tensile state of stress, while the PFET channel is usually in a compressive state of stress. The methods of fabrication include the deposition of metal layers by physical vapor deposition (PVD), in such manner that the layers are in stressed states.

Description

technical field [0001] The present invention relates to electronic devices. In particular, it relates to FET devices in which the channel region is under tensile or compressive stress. The invention also relates to methods for producing the above-mentioned structures by introducing stress metals into the gates of devices. Background technique [0002] Today's integrated circuits include a huge number of devices. Smaller devices and scaling rules are the keys to enhanced performance and lower costs. As the dimensions of FET (Field Effect Transistor) devices shrink, the technology becomes more complex requiring changes in device structure as well as new fabrication methods to maintain the desired enhancement in performance from one device generation to the next. The mainstream material for microelectronics is silicon (Si), or more broadly, Si-based materials. An important such Si-based material for microelectronics is the silicon-germanium (SiGe) alloy. [0003] There are...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/772H01L29/78H01L29/49H01L27/092H01L21/335H01L21/336H01L21/8238
CPCH01L21/823807H01L21/823842H01L29/4958H01L29/7845
Inventor B·B·多丽斯S·M·罗斯纳戈尔小西里尔·加布莱尔M·L·斯廷E·A·达奇
Owner INT BUSINESS MASCH CORP