Master device of two-wire bus providing release function for clock line and method thereof

A computer system and clock line technology, applied in the field of main control components to achieve high reliability

Inactive Publication Date: 2008-10-01
ATEN INT CO
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The clock port transmits a clock to the controlled component through the clock line

Method used

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  • Master device of two-wire bus providing release function for clock line and method thereof
  • Master device of two-wire bus providing release function for clock line and method thereof
  • Master device of two-wire bus providing release function for clock line and method thereof

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Embodiment Construction

[0019] Please refer to FIG. 1, which is a simplified block diagram of a two-wire bus according to the first embodiment of the present invention, and a pulse diagram of its data line 300 and clock line 200, wherein the master control element 102 of the two-wire bus has a clock line 200 release function. In the first embodiment, the controlled device 106 is coupled to the master device 102 through a two-wire bus. The main control element 102 includes a data port, a clock port and an output port. Generally, the output port can be implemented as a general purpose input output (GPIO) port. The data port transmits data to the controlled device 106 and receives data from the controlled device 106 through the data line 300 . The clock port transmits the clock generated by the master device 102 to the controlled device 106 through the clock line 200 . The output port shown in FIG. 1 is coupled to the clock line 200 by a connection line 104 .

[0020] Taking the inter-integrated cir...

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PUM

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Abstract

Disclosed is a master device which is capable of communicating with a salve device via a two-wire bus having a clock line and a data line. The master device includes a data port, a clock port and an output port. The output port is also coupled to the clock line. When the clock is held by the slave device for exceeding a predetermined stretching period, the output port can transmit at least one clock pulse generated by the master device to the slave device through the clock line to prevent transmission failure or data corruption. The master device checks each time whether or not a response is received via the data port after the output port transmits the clock pulse generated by the master device. The response represents that releasing the clock is confirmed. Then, the data port transmits a stop pulse after releasing the clock.

Description

【Technical field】 [0001] The present invention relates to a master control element of a two-wire bus, in particular to a master control element of a two-wire bus with the function of releasing a clock line, a computer system with the master control element and a releasing method thereof. 【Background technique】 [0002] A two-wire bus that transmits data via a clock line and a data line has now become a mainstream specification. For example: Inter-Integrated Circuit Bus (I2C), Embedded System Design (CAN-Bus) and System Management Bus (SMBus) and other data transmission specifications that support any integrated circuit technology. A data line (SDA) and a clock line (SCL) are used to transmit data between any components coupled to the two-wire bus, and each component connected to the two-wire bus has a unique address. When the two-wire bus began to develop, in a two-wire bus control system, only one component was defined as the main control component, and the other component...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/42H04L7/00
CPCG06F13/4291
Inventor 蔡廷鸿
Owner ATEN INT CO
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