Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

NMOS transistor and method for forming same

A transistor and pocket-shaped technology, applied in the field of NMOS transistors and their formation, can solve problems such as the influence of undisclosed NMOS transistor performance, and achieve the effect of improving the driving current capability

Active Publication Date: 2010-09-29
SEMICON MFG INT (SHANGHAI) CORP
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the prior art does not disclose the implantation of carbon ions at the position of the source / drain extension region to form a carbon ion doped region and its impact on the performance of NMOS transistors

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • NMOS transistor and method for forming same
  • NMOS transistor and method for forming same
  • NMOS transistor and method for forming same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0026] The invention provides an NMOS transistor and a forming method thereof, which increase the drive current of the NMOS transistor and reduce the leakage current while keeping the threshold voltage unchanged from the prior art.

[0027] First, the present invention provides a method for forming an NMOS transistor, comprising the following steps: sequentially forming a gate dielectric layer and a polysilicon gate on a semiconductor substrate, the gate dielectric layer and the polysilicon gate forming a gate structure; Implant carbon ions into the semiconductor substrate to form carbon ion doped regions; form source / drain extension regions on both sides of the gate structure and in the semiconductor substrate; form source / drain electrodes on both sides of the gate structure and in the semiconductor substrate , the depth of the carbon ion doped region is bounded between the surface of the semiconductor substrate and the source / drain; the semiconductor substrate is annealed to ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

An NMOS transistor comprises a grid structure, source / drain extension areas, source / drain electrodes and carbon ions doping areas, wherein the grid structure is arranged on a semiconductor substrate, the source / drain extension areas and the source / drain electrodes are located on both sides of the grid structure and in the semiconductor substrate, the carbon ions doping areas are located on both sides of the grid structure and in the semiconductor substrate, and the depth of the carbon ions doping areas is between the surface of the semiconductor substrate and the source / drain electrodes. Correspondingly, the invention further provides a method for forming the NMOS transistor. The NMOS transistor decreases the indirect band-gaps between silicon crystals by the introduction of the carbon ions doping areas around the source / drain extension areas, thereby affecting the shape of energy bands to increase electron mobility and to more easily excite the charged ions simultaneously. The NMOS transistor increases the current drive capability under the condition of keeping the threshold voltage unchanged.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an NMOS transistor and a forming method thereof. Background technique [0002] With the development of semiconductor devices to high density and small size, metal-oxide-semiconductor (MOS) devices are the main driving force, and driving current and hot carrier injection are the two most important parameters in the design. Traditional design achieves expected performance by controlling gate oxide, channel region, well region, source / drain extension doping shape, pocket implant region, source / drain implant shape and thermal budget, etc. . The implanted dopant ions are usually elements with three or five valence electrons. Few studies have focused on implanting elements with 4 valence electrons, including heavier ions such as germanium, as pre-amorphization implant materials to reduce channeling induced by subsequent low-doped source / drain implants (LDD) or pocket implants....

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78H01L29/36
Inventor 王津洲赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products