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High-speed wide-region multi-mode programmable frequency divider capable of adjusting dutyfactor

A wide-range, duty-cycle technology, used in synchronous pulse counters and other directions, can solve problems such as increasing power consumption and increasing circuit complexity, and achieve the effect of increasing the duty cycle, eliminating the impact, and improving the driving ability.

Inactive Publication Date: 2010-06-09
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this article uses a combination of two schemes to adjust the duty cycle, adding additional multi-bit half-adders and many gate circuits, which increases the complexity of the circuit and increases power consumption.

Method used

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  • High-speed wide-region multi-mode programmable frequency divider capable of adjusting dutyfactor
  • High-speed wide-region multi-mode programmable frequency divider capable of adjusting dutyfactor
  • High-speed wide-region multi-mode programmable frequency divider capable of adjusting dutyfactor

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Embodiment Construction

[0020] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0021] The high-speed and wide-range programmable frequency divider in the prior art is cascaded with traditional 2 / 3 frequency division units, and the mode control output signal Mo only needs to be fed forward step by step, so it has a strong speed advantage. Connected to the OR gate network and adding a digital terminal, the range of the frequency division ratio is expanded, making it an arbitrary programmable frequency divider, such as figure 1 , according to the maximum value of the required frequency division ratio, determine the total number of 2 / 3 frequency division units n: 2 n ≤Maximum frequency division ration+1 , and then determine the number n′ of 2 / 3 frequency division units that do not need to be connected forward in series according to the minimum frequency division ratio: 2 n′ ≤Minimum frequency division ration′+1 , e...

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Abstract

The invention provides a multimode programmable frequency divider which has high speed and wide range and is capable of adjusting the duty ratio, comprising a main divider stage formed by a cascaded 2 / 3 frequency dividing units and a series of or gates used for expanding the range of frequency division, a control stage and an output stage circuit. The multimode programmable frequency divider guarantees the high speed property of the cascade of the prior 2 / 3 frequency dividing units, increases the pulse width of an output signal, removes the influence of the cycle of the input signal on the pulse width of the output signal, is provided with a small number of and gates or the or gates serving as the control stage or the output stage, improves the dutyfactor of the output signal, and ensuresthat the dutyfactor is controlled to between 33.3 and 66.6 percent; when the division ratio is 2<n>, the dutyfactor is 50 percent; when the division ratio is 2<n>-1, the dutyfactor approaches 50 percent with the increase of n; under the specific division ratio, the dutyfactor is 33.3 percent or 66.6 percent in the limit condition; compared with the common programmable frequency divider with high speed and wide range, the multimode programmable frequency divider greatly improves the driving ability.

Description

technical field [0001] The invention relates to the design of a frequency divider, in particular to the technical field of designing a high-speed and wide-range multi-mode programmable frequency divider, in particular to a high-speed and wide-range multi-mode programmable frequency divider with duty cycle adjustment. Background technique [0002] High-performance programmable frequency dividers are widely used in radio frequency and high-speed digital integrated circuits. High operating frequency, wide frequency division ratio range, low power consumption, large drive capacity, etc. are usually the general requirements of the system for frequency dividers. In July 2000, the article "A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology" published on pages 1039 to 1045 of IEEE "Journal of Solid-State Circuits" (JSSC), disclosed a high-speed low-power Programmable frequency divider circuit structure with wide frequency division ratio ra...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K23/50
Inventor 吴建辉王声扬李红张萌吉新村黄福青李闯
Owner SOUTHEAST UNIV