Three-dimensional stacking encapsulation method based on silicon through-hole

Abstract

The invention discloses a three-dimensional stacking and packaging method based on silicon through-holes, and relates to an integration technology in the semi-conductor field. The method comprises thefollowing steps: wafers to be packaged are provided, and each wafer is provided with a plurality of welding pads; etching process is carried out for blocking layers deposited on the faces of the wafers until the welding pads on the wafers are exposed; silicon through-holes are formed in positions corresponding to the welding pads; electrodeless plating is adopted for filling the silicon through-holes with metal, and ends of through-holes filled with the metal are electrically connected with the welding pads, and the other ends thereof extend from the backs of the wafers to form connection parts; electrodeless plating is used for plating the welding pads with metal, and the plated metal protrudes from the faces of the wafers to form connection parts; and wafer bonding equipment is utilizedfor bonding the connection part onto the face of one wafer with the connection part on the back of another wafer, and then stacking the two connection parts up. Compared with the prior art, in the method provided by the invention, the electrodeless plating technology is adopted for filling the silicon through-holes with the metal, thereby simplifying the packaging process and improving the reliability of the stacked wafers.

Description

technical field [0001] The invention relates to the integration technology in the field of semiconductors, in particular to a three-dimensional stack packaging method based on through-silicon vias. Background technique [0002] Consumer products, such as digital cameras, PDAs and mobile phones, and next-generation servers have higher and higher requirements for product miniaturization: functionality needs to be enhanced, storage capacity must be increased, and the package shape of memory and processors must be reduced. In order to meet this requirement, many device manufacturers have begun to study three-dimensional interconnection technology to stack chips. [0003] At present, the three-dimensional stack packaging technology based on copper-filled silicon vias has been widely used in the production process of semiconductors. The three-dimensional packaging method based on copper-filled TSVs generally includes the following steps: forming TSVs; depositing a barrier layer (...

AI Technical Summary

Problems solved by technology

Using the above packaging method requires the step of depositing copper seeds, and the process is more complicated; and the uniformity of copper seed deposition has a great influence on electroplating, and the process requirements are very high; in addition, when electroplating through holes with a large depth-to-width ratio, the opening is easy Premature sealing will cause holes in the through holes. The resistance of the through holes formed in this way is high, and the substances remaining in the holes during electroplating may be corrosive, which will affect the reliability of the through holes.

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