Time clock recovery system and method
A technology of clock recovery and local clock, applied in lighting devices, light sources, instruments, etc., can solve the problems of reducing cascade transmission rate, reducing system anti-interference ability, reducing system display performance, etc.
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Embodiment 1
[0041] Such as image 3 As shown, the present invention provides a clock recovery system, the system includes a local clock module and a clock signal extraction module, the local clock module provides a local clock signal for the clock signal extraction module, and the clock signal extraction module includes a counter 1, a counter 2, Divider 1, divider 2 and clock output unit, wherein, counter 1 counts the number of local clock cycles included in the continuous n-bit cascaded serial input signal sin, obtains the first counting result time_last, and sends time_last to Divider 1, wherein the value of n is preset by the system; divider 1 divides the value of time_last by n to obtain the second counting result time_last_ave, and sends time_last_ave to divider 2; counter 2 serially inputs the signal to each bit The number of local clocks contained in sin is counted to obtain the counting result cnt, and cnt is sent to divider 2; divider 2 obtains the ratio clk_choose according to t...
Embodiment 2
[0046] The present invention provides a clock recovery method, which includes the following steps: the local clock module provides a local clock signal with the same frequency to the clock signal extraction module; the counter 1 uses the local clock signal, and presets a fixed number of cascaded inputs to the system Count the number of local clocks contained in the accumulated signal to obtain the first counting result time_last; counter 2 uses the local clock signal to count the number of local clocks contained in each input signal to obtain the second counting result; divider 1 according to the first A counting result calculates the number of local clocks contained in the average input signal per bit in the preset fixed-digit input signal to obtain a third counting result time_last_ave; the divider 2 calculates the second counting result and the first counting result The ratio of the three count results to clk_choose.
[0047] Then, when the ratio is the first preset value, ...
Embodiment 3
[0052] As a signal protocol method, on the basis of Embodiment 2, such as figure 2 As shown, the cascaded input signal uses a pulse signal of a complete cycle as 1 bit, that is, a bit of data contains high level and low level. In this way, it is beneficial to improve the accuracy of clock signal extraction.
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