Fault-tolerance memory and error-correction error-tolerance method

Abstract

The invention relates to a fault tolerant memory and an error-correction fault-tolerant method thereof. The fault tolerant memory comprises a first-layer memory array, a first-layer decoding logic, a public redundant row, a public redundant line and a first-layer memory error-correction fault-tolerant circuit; the first-layer memory array consists of a plurality of zero-layer memories; the zero-layer memories comprise a zero-layer memory array, a zero-layer decoding logic, a private redundant row, a private redundant line and a zero-layer memory error-correction fault-tolerant circuit; and the zero-layer memory array consists of a plurality of memory words. The error-correction fault-tolerant method is as follows: first, a fault is replaced by the private redundant row and the private redundant line on the zero layer, but if the fault can not be replaced, the fault is replaced by the public redundant row and the public redundant line on the first layer. The method has the advantages of reducing the dependence of the memory on test apparatuses and repair apparatuses, and lowering the cost of the memory; and the memory has excellent repair efficiency and the method helps improve the memory yield.

Description

Technical field [0001] The present invention relates to the technical field of memory fault tolerance. Specifically, the present invention relates to a fault-tolerant memory and an error-correction and fault-tolerant method thereof. Background technique [0002] As the VLSI process continues to advance to the nanometer level, the requirements for chip size and performance are also constantly increasing. It can be seen from Moore's Law that the speed and performance of chips double every 18 months, the density of integrated circuits is also advancing at a rate of double every two years, and embedded memory gradually becomes the main body of integrated circuit chips. While the integrated circuit manufacturing technology has shortened the geometric area of ​​the circuit, even if the memory bit defect density continues to decrease with the continuous improvement of the process-less than 1%, or even less than 0.1%; but the failure density of the memory circuit level does not stay At t...

AI Technical Summary

Problems solved by technology

However, this method simply adds a small number of row / column redundant devices to the large memory. In the case of high defect density, limited by the distribution of redundant devices, a large number of failed memory cells cannot be effectively replaced.

And the use of this redundant replacement brings delay overhead, which greatly reduces the performance of the memory

Images