Method and system for generating test vector of chip technology regulation
A test vector and process adjustment technology, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problem of time-consuming and inaccurate test vector generation, and achieve the effect of increasing the generation speed
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[0036] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
[0037] refer to figure 2 , The system for generating test vectors for chip process adjustment according to the embodiment of the present invention includes: a static timing analysis device, a path analysis device, a simulation device, a path drive detection device, a judging device and a test vector generation device.
[0038] The static timing analysis device is used for performing static timing analysis on the chip according to the netlist and constraints, and generating a static timing analysis report. The static timing analysis report includes critical timing path information on each clock domain, and sampling information (that is, output signals) of each node in the critical timing path. When the netlist input to the static timing analysis de...
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