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Method and system for generating test vector of chip technology regulation

A test vector and process adjustment technology, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problem of time-consuming and inaccurate test vector generation, and achieve the effect of increasing the generation speed

Inactive Publication Date: 2009-06-24
ST ERICSSON SEMICON BEIJING
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AI Technical Summary

Problems solved by technology

[0005] The disadvantage of the existing technology is that it needs to manually look at the waveform for analysis, and the generation of test vectors is time-consuming and inaccurate

Method used

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  • Method and system for generating test vector of chip technology regulation
  • Method and system for generating test vector of chip technology regulation
  • Method and system for generating test vector of chip technology regulation

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Embodiment Construction

[0036] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] refer to figure 2 , The system for generating test vectors for chip process adjustment according to the embodiment of the present invention includes: a static timing analysis device, a path analysis device, a simulation device, a path drive detection device, a judging device and a test vector generation device.

[0038] The static timing analysis device is used for performing static timing analysis on the chip according to the netlist and constraints, and generating a static timing analysis report. The static timing analysis report includes critical timing path information on each clock domain, and sampling information (that is, output signals) of each node in the critical timing path. When the netlist input to the static timing analysis de...

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Abstract

The invention provides a method and a system for testing vector quantity in the adjustment of chip producing process. The method comprises the following steps: A, static timing analysis is performed on a chip according to a net list and restrictions; B, analysis is performed on a static timing analysis report, so as to produce a report file comprising output signals of each node in a key timing path and the path; C, simulation is performed on the net list of the chip through the running of a functional test procedure, and a wave file is output; D, Whether the key timing path is driven completely can be adjusted according to the report file and the wave file; if the key timing path is driven completely, the step E is taken; and if not, the starting point and the end point of the partially driven path are recorded, and turning back to step A after the starting point and the end point are added into the restriction; and E, test vector is produced according to the wave file when the completely driven key timing path meets the requirements of the process adjustment. By adopting the invention, simulation waveforms are not required to be analyzed manually, the test vector can be produced automatically, and the producing speed for the test vector is effectively improved.

Description

technical field [0001] The invention belongs to the technical field of chip design and testing, and in particular relates to a method and system for generating test vectors for chip process adjustment. Background technique [0002] When the function of the chip design reaches the design index and large-scale mass production is carried out, the functional test of the chip is an indispensable link. refer to figure 1 , the current chip performance test is mainly to generate test vectors by simulating the chip netlist through computing equipment; then download the test vectors to the testing machine; the testing machine drives the input signal of the chip according to the test vector, and simultaneously detects the output signal of the chip According to the comparison between the output signal of the chip and the test vector, it can be known whether the chip can work normally. [0003] Process adjustment is an essential process before mass production of chips. It first produce...

Claims

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Application Information

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IPC IPC(8): G06F17/50G01R31/3183
Inventor 梁洪崑樊小波王平平
Owner ST ERICSSON SEMICON BEIJING
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