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Network-on-chip router having adaptive routing capability and implementing method thereof

An on-chip network and router technology, which is applied in the field of on-chip multi-processor inter-core communication, can solve problems affecting performance, resources cannot be fully utilized, data packet blocking, etc., and achieve the effects of improving efficiency, facilitating efficient interaction, and reducing blocking

Inactive Publication Date: 2011-01-26
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, there will be such a situation that there are multiple data packets in a router requesting the right to use port east, but some data packets can also reach the destination through port north and port north is idle at this time, so that resources cannot be used. Fully utilized, data packets are blocked, affecting overall performance

Method used

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  • Network-on-chip router having adaptive routing capability and implementing method thereof
  • Network-on-chip router having adaptive routing capability and implementing method thereof
  • Network-on-chip router having adaptive routing capability and implementing method thereof

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Embodiment Construction

[0029] The invention proposes an on-chip router design method with self-adaptive routing capability, which is used to construct an on-chip network communication system. In the process of designing the router, such as figure 1 structure shown. The invention designs the processes of receiving, buffering, analyzing routing, forwarding and the like of the data packets respectively.

[0030] Packet format used

[0031] The following data packet format is adopted in the present invention, as figure 2 As shown, it includes four parts: address in X direction, address in Y direction, data and data type. Wherein, the data width of the X and Y addresses determines the size of the network that the current router can support. For example, if the data width of X and Y is 4, then the largest network supported by the current router is 16×16. Data and data types determine the content and properties of the data communicated between endpoints.

[0032] Input Stream and Output Stream Contr...

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PUM

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Abstract

The invention relates to the technical field of on-chip multiprocessor internuclear communication, which aims to provide an on-chip network router having adaptive routing ability and implementation method thereof, used for constructing an on-chip network communication system. The on-chip network router comprises an input controller, an input buffer, a route moderator, an output controller and an output stream controller that are sequentially connected; the input buffer comprises a data register set in turn and a data selector, and a data packet pointer is connected with the data selector. In the invention, the route process has certain adaptivity by using an advanced XY router, thereby being capable of dynamically selecting proper data ports according to the congestion degree of data ports, reducing congestion of data packets, and improving the transmission speed and thuoughput of network. The application of modularized design method can reduce the complexity of design, thereby improving the efficiency of module function verification. The design of ports between modules simplifies the module design, thereby being convenient for high-efficient interaction between the modules.

Description

technical field [0001] The invention relates to the technical field of on-chip multi-processor inter-core communication, and proposes an on-chip network router with self-adaptive routing capability and an implementation method thereof, which are used to build an on-chip network communication system. Background technique [0002] With the development of computer manufacturing and integrated circuit technology, the number of transistors on a unit silicon chip has doubled, which means that more processor cores can be integrated on a unit silicon chip area. On-chip multi-core, that is, an architecture that implements multiple processor cores on a single silicon chip, is gradually favored by the industry due to its simplicity in design and verification, as well as its advantages in performance and energy consumption. [0003] An important problem in single-chip multiprocessor is the communication connection between processors. The traditional method is to use a shared bus, that ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/56H04L29/06H04L45/60
Inventor 陈天洲章铁飞项凌翔缪良华王春昊曹满马建良黄江伟乔福明陈度
Owner ZHEJIANG UNIV
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