Signal delay circuit

Abstract

The invention discloses a signal delay circuit, comprising a capacitance load component. The component is provided with a first input end, a second input end and a third input end; wherein, the first input end receives a first signal; the second input receives a second signal which is an inversion signal of the first signal; and the third input end receives a control signal; wherein, the capacitance value of the capacitance load component is changed with the control signal.

Description

technical field [0001] The invention discloses a capacitive load component, in particular to a capacitive load component used in a signal delay circuit. Background technique [0002] Regarding the digital control delay circuit (digital control delay element), it can be divided into an analog delay circuit and a digital delay circuit in terms of structure and adjustment mechanism. [0003] The analog delay circuit is characterized by an analog control signal plus an analog delay circuit. A common analog delay circuit includes a digital-to-analog circuit and a delay circuit. The digital control signal converts the external digital control signal into an analog voltage through a digital to analog conversion circuit (Digital to Analog Converter, DAC). The delay circuit is composed of a differential pair circuit composed of N-type transistors or P-type transistors with different load resistors or load capacitors. By slightly adjusting the parameters in the delay component, such...

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Problems solved by technology

It can be seen from the figure that due to the change of the control signal, the transmission delay of this circuit will increase due to the increase of the parasitic capacitance value

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