Built-in self-test method of FPGA logical resource

Abstract

The invention provides a built-in self-test method of FPGA logical resource. The internal logical module of FPGA is alternately divided into a left half part and a right half part according to row. In the test process, the logical module array of the right half part is firstly configured as a to-be-tested circuit, and the rest logical module arrays are configured as a test vector generating circuit and an output response analyzing circuit, and then the logical module array of the left half part is configured as the to-be-tested circuit, and the rest logical module arrays are configured as thetest vector generating circuit and the output response analyzing circuit. The circuit structure is not changed in each process. The logical resource is covered by multiple configurations and the testresult is output by a built-in scan register chain. All configurations in the invention are as follows: all logical modules configured as the response analyzing circuits are in cascade connection endto end according to one-dimensional array, so as to simplify the self-test result retrieval manner. Provided that the test coverage is 100%, the built-in self-test method reduces times of the configurations of FPGA logical resource, reduces test cost and increases test flexibility, so as to improve test efficiency.

Description

technical field [0001] The invention relates to a testing method of an FPGA chip, in particular to a built-in self-testing method based on scanning register FPGA logic resources. Background technique [0002] FPGA testing takes advantage of its reprogrammable feature to cover all resources under test through multiple configurations. There are mainly two methods for testing it: external testing and built-in self-testing. During external testing, the FPGA device is configured as a corresponding testing circuit, and external equipment is used to apply test vectors and special equipment to analyze the output results. This method occupies a large number of pins, resulting in The test depends on the package; compared with the external test, the vector application and response analysis of the built-in self-test method are completed internally, without the need for special test equipment and a large number of pins, which reduces the test cost and increases the test flexibility. [...

AI Technical Summary

Problems solved by technology

However, the article only briefly introduces the basic structure of FPGA logic BIST, and gives the general and common steps of BIST test structure, but does not make a further in-depth introduction to the method

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