22 results about "Partial logic" patented technology

The invention belongs to the field of integrated circuit fault analysis, and particularly relates to a large-scale integrated circuit multi-means combined soft defect fault positioning method, which comprises the following steps of: narrowing a multi-input vector range by adopting a dichotomy, and quickly determining a part of logic vectors associated with a fault phenomenon; the method comprises the following steps: dividing an internal transistor of a large-scale integrated circuit into a plurality of functional modules according to functions, and testing each functional module in a grading manner in combination with a nanoprobe and a dichotomy under the excitation of a part of logic vectors associated with a fault phenomenon; for the screened abnormal function modules, whether transistor faults or / and connecting line faults exist or not is judged; if a transistor fault or / and a connecting line fault exist, scanning the fault transistor and an accessory line by adopting an SEM, slicing a fault part by adopting an FIB, and observing the fault morphology by adopting a TEM; according to the method, the positioning range is effectively narrowed, fault excitation conditions are refined, soft errors in a large range are converted into hard errors in a small range, and then fault points are quickly positioned.

The embodiment of the invention provides an FPGA (Field Programmable Gate Array) function reconstruction method and device, electronic equipment and a storage medium, relates to the technical field of hardware, is applied to an FPGA node controller, and comprises the following steps: receiving a function reconstruction instruction sent by a management server; from a plurality of vFPGAs in the FPGA, a target vFPGA for which the function reconstruction instruction aims is determined, and each vFPGA comprises a part of logic resource blocks in the FPGA; and controlling the target vFPGA to read a target function parameter file indicated by the function reconstruction instruction, and enabling the target vFPGA to perform function reconstruction based on the target function parameter file. By applying the scheme provided by the embodiment of the invention, FPGA function reconstruction can be realized.

The invention discloses a metadata space management method, device and equipment and a readable storage medium, and relates to the technical field of computers, the method comprises the following steps: selecting a target metadata service as a default metadata service; the default metadata service is used for distributing the logic space of the management storage pool; when the metadata spaces of other metadata services except the target metadata service are lower than a lower use limit threshold value, sending a space application instruction to the target metadata service; and after the target metadata service responds to the space application instruction and distributes part of logic space of the storage pool to other metadata services, the other metadata services store the distributed space as own metadata space. In this way, the metadata service manages the metadata space, management of the metadata service space of multiple nodes is achieved only through one storage pool, and no longer depends on an object storage daemon process and reliable and automatic distributed object storage.

The embodiment of the invention provides a test case generation method and device, a storage medium and a program product. In the embodiment of the invention, in the process of converting the historical path record of the UI automatic test into the structured knowledge graph, semantic modeling of the path unit is realized through the entity relationship template, so that the test logic has a cross-device and cross-version abstract reuse capability, and most logic can still be reused when the actually measured display interface element changes; a page-element-relation triple is automatically extracted by using a large language model, and a queriable three-dimensional network structure is constructed, so that the complex path analysis efficiency is greatly improved; based on the dynamic reasoning ability of the knowledge graph, advanced test cases for abnormal path detection, behavior prediction and the like can be automatically generated, and the case design time is remarkably shortened. Therefore, cross-version, cross-device or cross-resolution multiplexing of the test case is realized, the test efficiency can be improved, and the test cost can be reduced.

A stack of memory chips and a logic chip is placed within a same package. Multiple memory chips of the stack of memory chips are divided into fractions, and multiple internal channels within the package that emanate from the logic chip are coupled to respective ones of the fractions. The logic chip has a multiplexer, including a multiplexer to multiplex a single input / output (I / O) channel of the package to the multiple internal channels.

The invention discloses an automatic script processing method and device, and relates to the technical field of automatic processing, when a user interface is changed, a system can perform locator incremental update on an initial automatic test script through a preset incremental update mode and a key user interface change list, and the user interface change list is updated. According to the method, the script locators and part of logics are automatically adjusted, so that the workload of manual intervention and manual user interface automatic test script reconstruction is greatly reduced, the script maintenance cost is reduced, the test period is shortened, and the adaptability in the user interface automatic test process is improved. A path entropy concept and a preset intelligent path recommendation mode based on multi-feature time sequence modeling are introduced to carry out automatic test path recommendation, so that a test path which has higher stability and higher robustness and can effectively cover key service nodes can be intelligently recommended; and the robustness of visual change in the process of automatically testing the user interface is improved.

The embodiment of the invention discloses an Internet of Things system and a control method thereof, and the Internet of Things system of the embodiment of the invention comprises a plurality of functional devices and at least one gateway device, the gateway device is controlled to deploy the chained control logic so as to control the corresponding function device to execute the corresponding target action according to the chained control logic based on the received state information of each function device, and each function device is controlled to deploy the corresponding target control logic step by step. After deployment is completed, corresponding target actions are executed on the basis of the target control logics deployed by the functional devices and the state information of the functional devices, the chain control logics represent the chain control relation between the functional devices, and the target control logics are part of logics in the chain control logics. Therefore, according to the embodiment of the invention, the gateway equipment can be used for executing the distributed chained control process in a dynamic proxy manner, and the dynamic deployment scheme is used for deploying the control logic to the functional equipment, so that the configuration efficiency is improved, and the automatic execution experience is ensured.

Embodiments of the present disclosure relate to partition aware broadcast operation filtering in a multiprocessor system. Various embodiments include techniques for processing broadcast operations in a computing system. Typically, broadcast operations are sent to all portions of a particular subsystem, such as all cache slices in cache memory, etc. Thus, a process that issues a broadcast operation may interfere with one or more other processes that access portions of the subsystem that are not allocated to the process. To prevent such interference, logic in the computing system filters broadcast operations in order to send broadcast operations to relevant portions that are only allocated to processes that emanate the broadcast operations. The logic tracks acknowledgements from the relevant portion and when all suspended acknowledgements have been received, the logic sends a single acknowledgement to the process issuing the broadcast operation. The logic is dynamically configurable such that the logic can change portions of the subsystem allocated to each process as needed.

Systems, apparatuses, and methods are provided for logical-to-physical (L2P) address translation. A method may include receiving a request for a first logical data address (LDA), computing a first translation data unit (TDU) index for a respective first TDU. The first TDU may contain an L2P entry for a corresponding first LDA. The method may further include using a first TDU index to search for a cache of a lookup directory entry of the most recently accessed TDU, determining that there is a missed cache, generating and storing in the missed cache a pending request for the lookup directory entry of the corresponding first TDU, obtaining the lookup directory entry of the corresponding first TDU from the in-memory lookup directory, and storing the obtained lookup directory entry of the corresponding first TDU from the in-memory lookup directory. And determining that the lookup directory entry of the corresponding first TDU is invalid, reserving a TDU space of the corresponding first TDU in a memory, and generating a loading request of the corresponding first TDU.

A storage system caches logical-to-physical address table entries read in volatile memory. The logical-to-physical address table entries are stored in codewords. The storage system can change the number or size of entries in a codeword. Additionally or alternatively, each codeword can store both a full logical-to-physical address table entry and a partial logical-to-physical address table entry. In one example, a codeword with 62 bytes of data and two bytes of error correction code stores 15 full logical-to-physical address table entries and one partial logical-to-physical address table entry, with the remainder of the partial entry stored in another codeword. This configuration achieves a good balance between storage space efficiency and random access write performance.

The invention relates to the technical field of communication, and provides an SRv6 traffic forwarding device, method and equipment, a medium and a program product, and the device comprises a network card which is used for receiving a data packet and forwarding the processed data packet; the first processing module is a programmable logic device and is used for processing the first type of data packets; the second processing module is a non-programmable logic device and is used for processing the second type of data packets; the logic complexity of the second type of data packets is higher than that of the first type of data packets. Data packets with low logic complexity are processed through the first processing module realized by hardware, high performance of traffic forwarding by hardware is realized, a small part of data packets with high logic complexity are processed through the second processing module realized by software, and flexibility and evolution of traffic forwarding by software are realized. The method supports huge flow of key nodes of a backbone network in a soft and hard combination mode by supporting a complex function chain of a protocol, and rapidly adapts to dynamic changes of services.

The application discloses a memory-compute FPGA architecture. Memory-compute cores, memory blocks and logic function blocks used for replacing part of the logic function blocks are arranged in a row-column array and arranged in an island type architecture. In the memory-compute cores, there are SRAMs arranged in a row-column array, the SRAMs store one-bit data, the output ends of an address decoding circuit are connected with each row of the SRAM array, the output ends of a write control circuit are connected with each column of the SRAM array, each eight columns of the SRAM array and an input register are connected with an 8-bit input port of an addition tree through a multiplexer and eight NOR gates, and the output port of the addition tree is connected with an output register through a shift and addition module and a quantization module in sequence. The application realizes in-memory computation on the FPGA, utilizes the parallelism and reconfigurability of the FPGA to support mapping of various networks, and utilizes in-memory computation technology to reduce data movement and further reduce computation power consumption.

Embodiments of the present disclosure relate to a semiconductor device. According to the embodiments of the present disclosure, a memory controller is capable of efficiently managing error detection data and may include an error detection circuit configured to externally receive write data and a plurality of logical addresses corresponding to the write data, and generate error detection data corresponding to the write data, a data compression circuit configured to compress the write data to generate compression data corresponding to partial logical addresses among the plurality of logical addresses, and a map data controller configured to manage map data including a mapping relationship between the plurality of logical addresses and physical addresses of a memory device, and store physical addresses mapped to the partial logical addresses, the error detection data, and compression information related to the compression data in the map data.

Embodiments of the present disclosure relate to a memory controller, an operating method thereof, and a memory device including the same. According to an embodiment of the present disclosure, a memory controller can effectively manage error detection data, and may include: an error detection circuit configured to receive write data from outside and generate error detection data corresponding to the write data; a data compression circuit configured to compress the write data to generate compressed data corresponding to partial logical addresses among a plurality of logical addresses, the plurality of logical addresses corresponding to the write data; and a mapping data controller configured to manage mapping data including a mapping relationship between the plurality of logical addresses and a physical address of the memory device, and store the physical address mapped to the partial logical address, the error detection data, and compression information related to the compression data in the mapping data.

To enable setting of preventing deterioration of output accuracy from being quickly recovered even if being out of the setting of preventing deterioration of output accuracy and to enable a plurality of comparators having different characteristics to be appropriately used.SOLUTION: A comparison circuit (13) includes first and second comparators (131, 132) and a logic part (134). The logic part adjusts a variable reference voltage to make logic switching timing of a second comparison signal outputted from the second comparator come close to logic switching timing of a first comparison signal outputted from the first comparator. The comparison circuit has an up-down counter (133a), divides a counter value of the up-down counter into a higher-order bit side and a lower-order bit side in adjusting the variable reference voltage, changes a value of the higher-order bit side to narrow down the adjustment range of the variable reference voltage, and changes a value of the lower-order bit side within the narrowed-down adjustment range.SELECTED DRAWING: Figure 4

The invention discloses an acceleration device and method for calculating a Gamma correction algorithm, which can remarkably improve the execution speed of the Gamma correction algorithm and effectively solve the bottleneck problem of a traditional general processor in the aspect of processing efficiency. The device comprises a value taking unit, a decoding unit, an execution unit, a memory access unit and a write-back unit, the valuing unit comprises an instruction memory, a program counter, an instruction prefetching unit, a branch prediction unit and a pre-decoding unit; the execution unit comprises a branch instruction module, an ALU module, an MUL module, a DIV module, an FPU module and a GAMMA unit which shares partial logic resources with the ALU module and the FPU module; the memory access unit comprises a data memory; the write-back unit comprises an integer register file GPR and a floating point register file FPR.

The application discloses a data replication method based on a logical volume. The method comprises the following steps: determining a replication cache calling function according to a target disk corresponding to a logical volume to be replicated in a production machine; replicating the logical volume to be replicated by using the replication cache calling function to obtain replication data; determining disk data fragments corresponding to the replication data based on a linear mapping mechanism or a strip mapping mechanism, and writing the disk data fragments into a disk of a disaster recovery machine. The technical scheme of the embodiment of the application can replicate data of a specified disk, solves the problem that a traditional replication mode does not support partial logical volume data replication, and converts the replication data of the logical volume into disk data fragments, so that the disk data fragments are replicated to an underlying disk of a logical volume of the disaster recovery machine, thereby avoiding the problem that partial applications are unavailable due to changes in the number and names of the disks of the disaster recovery machine and the production machine.

The invention discloses an automatic initialization module of a 1553B bus circuit based on an SPI (Serial Peripheral Interface), which belongs to the field of communication circuits and comprises an SPI control logic, a serial-parallel conversion unit, a cache unit, an address data separation unit, a register / memory instruction analysis module, a 1553B circuit initialization logic and a register and memory interface, so that the circuit has an automatic initialization function. After the circuit is powered on or an automatic initialization function is enabled through an external pin, an internal register and a memory automatically finish initialization configuration, and manual operation is not needed. According to the invention, the basic structure of the original 1553B circuit is not changed, and only a part of logic is needed to be added for automatic initialization control and interfaces, so that the correctness and comprehensiveness of the initialization time sequence are ensured, the difficulty of using the 1553B bus circuit by a user is greatly reduced, and the development efficiency is improved.

Systems, apparatus, and methods for logical-to-physical (L2P) address translation are provided. A method may include receiving a request for a first logical data address (LDA), calculating a first TDU index for a corresponding first translated data unit (TDU). The first TDU may include an L2P entry for the corresponding first LDA. The method may further include searching a cache of lookup directory entries for a recently accessed TDU using the first TDU index, determining a cache miss, generating and storing a pending request for the lookup directory entry for the corresponding first TDU in a miss buffer, obtaining the lookup directory entry for the corresponding first TDU from an in-memory lookup directory, determining that the lookup directory entry for the corresponding first TDU is invalid, reserving TDU space for the corresponding first TDU in memory, and generating a load request for the corresponding first TDU.

This invention relates to a circuit structure for implementing phase lead-lag commutation in a motor. The circuit structure includes a Hall angle mapping module for receiving three Hall signals generated by an external motor's Hall module and configuring them into Hall synchronization angle values; a Hall angle update module for selecting an appropriate angle update mode based on the circuit structure's internal logic; a three-phase angle generation module for performing time-division calculations on the angles generated by the Hall angle update module to generate the current three-phase angle signal; an angle conversion module for performing corresponding angle conversions on the three-phase angle signal generated by the three-phase angle generation module; and a PWM generation module for generating a three-phase, six-channel complementary PWM waveform. The circuit structure of this invention only adds a few logic circuit modules, yet it can easily implement phase lead-lag operation and achieve smooth switching between square wave and sine wave control modes.

Examples relate to an apparatus, device, method, and computer program for generating logic to be performed by computing circuitry of a computing architecture. The apparatus is configured to determine a performance-critical compute path of a compute kernel to be executed on a plurality of units of computing circuitry of a computing architecture, the compute kernel comprising a plurality of interdependent groups of computational instructions, with the performance-critical compute path being based on a subset of the interdependent groups of computational instructions. The apparatus is configured to determine, for at least one group of computational instructions outside the performance-critical compute path, a reduced clock frequency being lower than a maximally feasible clock frequency of the respective group of computational instructions. The apparatus is configured to generate logic to be performed by one or more of the plurality of separately controllable units of computing circuitry based on the compute kernel, wherein a portion of the logic that is generated to be performed by the plurality of separately controllable units of computing circuitry outside the performance-critical compute path is generated based at least in part on the reduced clock frequency.

An acceleration device and method for calculating a gamma correction algorithm can significantly improve the execution speed of the gamma correction algorithm, effectively resolving bottlenecks in processing efficiency in traditional general-purpose processors. The device comprises a value acquisition unit, a decoding unit, an execution unit, a memory access unit, and a write-back unit. The value acquisition unit includes an instruction memory, a program counter, an instruction prefetch unit, a branch prediction unit, and a pre-decoding unit. The execution unit includes a branch instruction module, an ALU module, a MUL module, a DIV module, an FPU module, and a gamma unit that shares some logical resources with the ALU and FPU modules. The memory access unit includes a data memory. The write-back unit includes an integer register file (GPR) and a floating-point register file (FPR).