7 results about "Partial logic" patented technology

The invention discloses an automatic script processing method and device, and relates to the technical field of automatic processing, when a user interface is changed, a system can perform locator incremental update on an initial automatic test script through a preset incremental update mode and a key user interface change list, and the user interface change list is updated. According to the method, the script locators and part of logics are automatically adjusted, so that the workload of manual intervention and manual user interface automatic test script reconstruction is greatly reduced, the script maintenance cost is reduced, the test period is shortened, and the adaptability in the user interface automatic test process is improved. A path entropy concept and a preset intelligent path recommendation mode based on multi-feature time sequence modeling are introduced to carry out automatic test path recommendation, so that a test path which has higher stability and higher robustness and can effectively cover key service nodes can be intelligently recommended; and the robustness of visual change in the process of automatically testing the user interface is improved.

A storage system caches logical-to-physical address table entries read in volatile memory. The logical-to-physical address table entries are stored in codewords. The storage system can change the number or size of entries in a codeword. Additionally or alternatively, each codeword can store both a full logical-to-physical address table entry and a partial logical-to-physical address table entry. In one example, a codeword with 62 bytes of data and two bytes of error correction code stores 15 full logical-to-physical address table entries and one partial logical-to-physical address table entry, with the remainder of the partial entry stored in another codeword. This configuration achieves a good balance between storage space efficiency and random access write performance.

The invention relates to the technical field of communication, and provides an SRv6 traffic forwarding device, method and equipment, a medium and a program product, and the device comprises a network card which is used for receiving a data packet and forwarding the processed data packet; the first processing module is a programmable logic device and is used for processing the first type of data packets; the second processing module is a non-programmable logic device and is used for processing the second type of data packets; the logic complexity of the second type of data packets is higher than that of the first type of data packets. Data packets with low logic complexity are processed through the first processing module realized by hardware, high performance of traffic forwarding by hardware is realized, a small part of data packets with high logic complexity are processed through the second processing module realized by software, and flexibility and evolution of traffic forwarding by software are realized. The method supports huge flow of key nodes of a backbone network in a soft and hard combination mode by supporting a complex function chain of a protocol, and rapidly adapts to dynamic changes of services.

The application discloses a memory-compute FPGA architecture. Memory-compute cores, memory blocks and logic function blocks used for replacing part of the logic function blocks are arranged in a row-column array and arranged in an island type architecture. In the memory-compute cores, there are SRAMs arranged in a row-column array, the SRAMs store one-bit data, the output ends of an address decoding circuit are connected with each row of the SRAM array, the output ends of a write control circuit are connected with each column of the SRAM array, each eight columns of the SRAM array and an input register are connected with an 8-bit input port of an addition tree through a multiplexer and eight NOR gates, and the output port of the addition tree is connected with an output register through a shift and addition module and a quantization module in sequence. The application realizes in-memory computation on the FPGA, utilizes the parallelism and reconfigurability of the FPGA to support mapping of various networks, and utilizes in-memory computation technology to reduce data movement and further reduce computation power consumption.

The application discloses a data replication method based on a logical volume. The method comprises the following steps: determining a replication cache calling function according to a target disk corresponding to a logical volume to be replicated in a production machine; replicating the logical volume to be replicated by using the replication cache calling function to obtain replication data; determining disk data fragments corresponding to the replication data based on a linear mapping mechanism or a strip mapping mechanism, and writing the disk data fragments into a disk of a disaster recovery machine. The technical scheme of the embodiment of the application can replicate data of a specified disk, solves the problem that a traditional replication mode does not support partial logical volume data replication, and converts the replication data of the logical volume into disk data fragments, so that the disk data fragments are replicated to an underlying disk of a logical volume of the disaster recovery machine, thereby avoiding the problem that partial applications are unavailable due to changes in the number and names of the disks of the disaster recovery machine and the production machine.

This invention relates to a circuit structure for implementing phase lead-lag commutation in a motor. The circuit structure includes a Hall angle mapping module for receiving three Hall signals generated by an external motor's Hall module and configuring them into Hall synchronization angle values; a Hall angle update module for selecting an appropriate angle update mode based on the circuit structure's internal logic; a three-phase angle generation module for performing time-division calculations on the angles generated by the Hall angle update module to generate the current three-phase angle signal; an angle conversion module for performing corresponding angle conversions on the three-phase angle signal generated by the three-phase angle generation module; and a PWM generation module for generating a three-phase, six-channel complementary PWM waveform. The circuit structure of this invention only adds a few logic circuit modules, yet it can easily implement phase lead-lag operation and achieve smooth switching between square wave and sine wave control modes.

Examples relate to an apparatus, device, method, and computer program for generating logic to be performed by computing circuitry of a computing architecture. The apparatus is configured to determine a performance-critical compute path of a compute kernel to be executed on a plurality of units of computing circuitry of a computing architecture, the compute kernel comprising a plurality of interdependent groups of computational instructions, with the performance-critical compute path being based on a subset of the interdependent groups of computational instructions. The apparatus is configured to determine, for at least one group of computational instructions outside the performance-critical compute path, a reduced clock frequency being lower than a maximally feasible clock frequency of the respective group of computational instructions. The apparatus is configured to generate logic to be performed by one or more of the plurality of separately controllable units of computing circuitry based on the compute kernel, wherein a portion of the logic that is generated to be performed by the plurality of separately controllable units of computing circuitry outside the performance-critical compute path is generated based at least in part on the reduced clock frequency.