60 results about "Partial logic" patented technology

A network tool is provided for use when replacing devices in an automatically controlled distributed processing system. The network tool reestablishes all or a portion of the logical connections formerly provided to the node where the replacement device is or will be located. The tool compares data associated with the logical connections of the node and data associated with the logical connections for the replacement device to determine proper logical connection. In one embodiment, the compared data comprises network variables and configuration properties.

Embodiments of the present invention provide a layout analysis method, comprising: extraction, collection of basic elements with respect to static area objects, analysis sequence determination and logical paragraph analysis, wherein the logical paragraph analysis comprises character analyzing, logical connection edge generating, line forming analyzing, paragraph forming analyzing, paragraph result filtering, basic elements collecting with respect to the dynamic area objects and basic element removing. According to the embodiments of the present invention, logical reference information and basic element data information are combined, and the logical reference information is fully used during layout analysis, such that a more accurate layout analysis result with respect to a fixed-layout document is acquired, and the layout analysis result is effectively improved.

Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Methods, systems and data structures produce a rasterizer. A graphical state is detected on a machine architecture. The graphical state is used for assembling a shell rasterizer. The machine architecture is used for selecting replacement logic that replaces portions of shell logic in the shell rasterizer. The machine architecture is used for selectively inserting memory management logic into portions of the shell logic to produce.

A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When programming the first portion of logic states, a first boosting process is applied to unselected memory cells and when programming the second portion of logic states, a second boosting process is applied to unselected memory cells.

A system for processing signals comprises a tuner and an input / output (IO) bus bridge, wherein the tuner and the IO bus bridge are formed at least in part on same semiconductor chip, and wherein at least a portion of logic on the chip is implemented in Complementary Metal Oxide Semiconductor (CMOS) logic, and wherein at least another portion of the logic is implemented with silicon germanium (SiGe) logic.

A signal capture element for providing a first pre-charged logic level as first and second interim address portion signals during a pre-charged period and outputting during an evaluate period an address portion logic level as the first interim address portion signal and an inverted address portion logic level as the second interim address portion signal. First and second address portion signals are derivable respectively from first and second interim address portion signals. An inverter circuit for outputting to an address decoder during a pre-charged period a second pre-charged logic level as the first and second address portion signals. The inverter circuit having transfer characteristics that maintain voltage levels such that the first and second address portion signals are interpreted to be at the second pre-charged logic level despite the first or second interim address portion signal failing to transition to a valid logic level during the evaluate period.

The invention provides a non-volatile memory device capable of improving the convenience of portable apparatus by reducing initialization time and the control method thereof. In generating the table of data validity at the time of initialization, the control section reads the validity flag and the second conversion table. When the validity flag is valid, the logical block of the second conversion table is also valid. Consequently, the fourth table generating means can set all the logical blocks on the second conversion table valid for the table of data validity. Therefore, the fourth table generating means can conduct setting of a plurality of logical blocks by reading only once as mentioned above. Furthermore, in regard to the partial logical block set valid for the table of data validity, reading of the validity flag can be omitted and be forwarded to process the next partial logical block.

The invention provides a built-in self-test method of FPGA logical resource. The internal logical module of FPGA is alternately divided into a left half part and a right half part according to row. In the test process, the logical module array of the right half part is firstly configured as a to-be-tested circuit, and the rest logical module arrays are configured as a test vector generating circuit and an output response analyzing circuit, and then the logical module array of the left half part is configured as the to-be-tested circuit, and the rest logical module arrays are configured as thetest vector generating circuit and the output response analyzing circuit. The circuit structure is not changed in each process. The logical resource is covered by multiple configurations and the testresult is output by a built-in scan register chain. All configurations in the invention are as follows: all logical modules configured as the response analyzing circuits are in cascade connection endto end according to one-dimensional array, so as to simplify the self-test result retrieval manner. Provided that the test coverage is 100%, the built-in self-test method reduces times of the configurations of FPGA logical resource, reduces test cost and increases test flexibility, so as to improve test efficiency.