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Computer interlocking system code bit-level redundancy method

A technology of computer interlocking and system code, applied in the redundancy of hardware for data error detection, interlocking device between switch and signal, transportation and packaging, etc., can solve the problem of not being able to complete normal work and affecting work efficiency. and other problems to achieve the effect of eliminating sudden shutdown, improving reliability, and alleviating reliability reduction.

Active Publication Date: 2009-11-18
CASCO SIGNAL
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  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

In this way of working, when the two systems have a cross fault that does not affect the system work at the same time, the two systems cannot complete the normal work.
For larger stations / fields, it will inevitably affect work efficiency

Method used

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  • Computer interlocking system code bit-level redundancy method
  • Computer interlocking system code bit-level redundancy method
  • Computer interlocking system code bit-level redundancy method

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0027] Hereinafter, taking the interlocking processing subsystem (IPS) of the iLOCK system as an example, the specific embodiments of the present invention will be described in detail in conjunction with the accompanying drawings.

[0028] output parallel control

[0029] Such as figure 1 As shown, the KZ and KF power sources drawn from the power panel are respectively sent to the IPS to generate the driving power for driving the related interface relays.

[0030] Output parallel control is implemented by application software. For the same driving relay, IPSA and IPSB respectively drive a group of coils of the relay. When the A-OUT and B-OUT of a certain output port are output at the same time, the parallel control of the port is realized. Otherwise, when the application software judges that a certain port cannot be controlled in parallel, it will close the output of the backup system of the port, and only the coils of the relays of the main system have driving power to real...

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Abstract

The invention relates to a computer interlocking system code bit-level redundancy method which comprises the following steps: output parallel control; and acquisition information sharing. Compared with the prior art, the invention can improve the reliability of the system, releases the pressure that the reliability is reduced in a computer system in a large station or a system with higher operation requirements to a certain extent and better stops the danger from generating due to train emergency braking as signals are cut off suddenly for reasons by adopting the measures of the output parallel control and the acquisition information sharing, especially aiming at the actual situation that the terminal wiring of a relay interface circuit in China has more faults and the situation that larger interference occurs in the station.

Description

technical field [0001] The invention relates to the field of signal interlocking of high-speed railways, ordinary railways and urban rail transit lines, in particular to a code-level redundancy method for computer interlocking systems. Background technique [0002] The computer interlocking system must control the approach, signals and switches under the specified interlocking conditions and the specified timing, and can collect status information. In order to improve system reliability and ensure 24-hour uninterrupted operation of the railway / urban rail transit system, computer interlocking should adopt a hardware safety redundant structure, such as a system structure of 2 by 2 (or 2 from 3) and dual-machine hot standby . [0003] The iLOCK interlocking processing subsystem adopts a dual-system hot-redundant 2x2-out system. Regardless of whether the A system and the B system are started at the same time, if the two systems have no faults and the synchronization check condi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B61L7/00
CPCB61L19/06G06F11/16
Inventor 凌祝军师秀霞
Owner CASCO SIGNAL
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