Encapsulation structure

Abstract

The invention provides an encapsulation structure, which comprises a cover plate, unit cavities, cutting ways, solder pad areas and clearance areas, wherein the unit cavities are positioned on the cover plate and discretely arranged; each unit cavity comprises a cavity and a unit cavity wall positioned on the periphery of the cavity; the cutting ways are positioned between adjacent unit cavities; the solder pad areas are positioned on edges of unit cavity walls and discretely arranged; the clearance areas are positioned in areas on the edges of the unit cavity walls excluding the solder pad areas; and corresponding edges of the unit cavity walls of the adjacent unit cavities are partially connected through the cutting ways. The corresponding edges of the unit cavity walls of the adjacent unit cavities are partially connected through the cutting ways on the cover plate, so the bonding force between the cavity walls and chips can be improved, and the problem that the mechanical stress generated in a subsequent V-shaped groove cutting process makes the cavity walls and the chips peel off to cause large-area yield loss is prevented.

Description

technical field [0001] The present application relates to the field of semiconductor packaging, in particular to a packaging structure. Background technique [0002] Wafer Level Chip Size Packaging (WLCSP) technology is a technology that performs packaging and testing on the entire wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is the same as that of the bare chip. Wafer-level chip-scale packaging technology has changed traditional packaging such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier), organic leadless chip carrier (Organic Leadless Chip Carrier) and digital camera module mode, in line with the market demand for microelectronics products Increasingly light, small, short, thin and low-cost requirements. The size of the chip packaged by the wafer-level chip size packaging technology has reached a high degree of miniaturization, and the cost of the chip is significantly reduced with the reduction of the chip siz...

AI Technical Summary

Problems solved by technology

But because the unit cavity walls 102, 202, 302, 402 are not bonded to the bonding pads 115, they are hollow, which relatively reduces the bonding force between the unit cavity walls 102, 202, 302, 402 and the wafer. The mechanical stress generated in the groove cutting process can easily cause the cavity wall to peel off from the wafer, resulting in a large area yield loss

Images