Base plate having pad-free type conductive traces and using for encapsulation

Abstract

The invention provides a base plate having pad-free type conductive traces and using for encapsulation. The base plate at least comprises a core plate layer and a plurality of conductive traces, wherein, the core plate layer is provided with a first surface and a second surface, and a plurality of plated through holes penetrating through the first surface and the second surface are formed in the core plate layer; a plurality of conductive traces are formed on the first surface of the core plate layer, and each conductive trace is provided with a connection end, an opposite welding pad end anda body connected with the connected end and the welding pad end; the connected ends are positioned on hole ends corresponding to the plated through holes so as to enable the conductive traces to be electrically connected with the plated through holes; and the width of the connected ends is greater than that of the bodies of the conductive traces but is not greater than the diameter of the plated through holes. Thereby, the contact area of the conductive traces and the plated through holes is increased, so that the crack problem generated at the contact faces of the conductive traces and the plated through holes is avoided.

Description

technical field [0001] The invention relates to a substrate for packaging, in particular to a substrate for packaging that is electrically connected to a plated through hole by means of a conductive trace. Background technique [0002] In order to overcome the problem that the signal transmission path of the chip is too long in the semiconductor packaging substrate used in the electronic device, the through hole (including the plated through hole (Pleated Through hole) as disclosed in Japanese Patent No. 11-008475 will be used in the circuit design. , PTH), micro-holes (Via) or blind holes, etc.) directly penetrate the substrate to shorten the conductive path, so as to improve the electrical quality of the highly integrated (High Integration) chip. [0003] figure 1 It is a schematic diagram of the first embodiment of the circuit lines and through holes of the existing substrate. As shown in the figure, it provides a substrate 100, and a through hole 101 through the surfac...

AI Technical Summary

Problems solved by technology

However, because this wet etching is isotropic (Isotropic) etching, the upper surface of the conductive material 230 is severely etched and deformed due to prolonged contact with the etchant during the etching operation (such as Figure 2C shown), and when performing subsequent temperature cycle tests (Thermal Cycling Test; TCT), various thermal stresses may be formed due to the influence of high temperature environment or rapid temperature changes, and then lead to the conductive material 230 and the circuit line 210 The contact surface 202 produces damage (crack) (such as Figure 2D shown)

And because the width of the circuit line 210 is small, when the contact surface 202 is damaged, it is easy to extend and break from one side of the contact surface 202 to the other side, thereby causing the circuit line 210 to peel off from the conductive material 230, etc. sexual problems

Furthermore, after etching, the terminal of the circuit line 210 forms a near right angle, so that the terminal of the circuit line 210 and the contact angle 203 at the intersection of the conductive material 230 and the circuit line 210 are likely to cause stress concentration problems (such as Figure 2E shown)

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