Sram with improved read/write stability

Abstract

A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.

Description

technical field [0001] The present invention relates generally to integrated circuit design and, more particularly, to static random access memory (SRAM) with improved read / write stability. Background technique [0002] SRAM is a memory that stores data in an array of cells, and it does not need to be constantly refreshed as long as it is powered on. figure 1 A conventional 6-transistor (6T) SRAM cell 100 is exemplarily shown, which includes pull-up devices 102 and 104 , pull-down devices 106 and 108 , and pass-gate devices 110 and 112 . The pull-up device 102 is a PMOS transistor, its source is coupled to the voltage source VDD, its drain is coupled to the drain of the pull-down device 106, and the pull-down device 106 is an NMOS device, its source is coupled to the power ground or VSS , the power ground or VSS can be any voltage value lower than the voltage source VDD. The pull-up device 104 is also a PMOS transistor, its source is coupled to the voltage source VDD, and ...

AI Technical Summary

Problems solved by technology

As a result, the data stored in those unselected cells is still disturbed by the voltages on their corresponding bit lines and complementary bit lines

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