Memory control method, memory controller and memory control system

Abstract

The invention discloses a memory control method, a memory controller and a memory control system, relating to the technique of memory control, fully using the advantages of a page keeping opening strategy and a page keeping closing strategy, reducing the reversion of read-write commands, largely reducing the delay of a memory in data access, obviously increasing the available bandwidth of a data bus and enhancing the system performance. The provided memory control method comprises the following steps: obtaining the running state of a storage body; obtaining the address information of a next command which corresponds to the storage body in a command queue to be executed; dynamically determining the current control strategy of the storage body according to the information of the running state and the address information; and the strategy comprises the page keeping opening strategy and the page keeping closing strategy. Simultaneously, the method also comprises the step: sequencing the commands in the command queue to be executed according to a preset sequencing rule. The memory control method is suitable for any scene for controlling the memory.

Description

technical field [0001] The invention relates to storage control technology, in particular to a storage control method, a storage controller and a storage control system. Background technique [0002] With the development of integration technology, individual chips in traditional technology can be integrated on one chip. For example, in the high-definition television (HDTV) system-on-chip (SOC) design, the technology of integrating each single chip, such as CPU, audio and video decoding unit, memory, display device and peripheral interface, etc., into a single chip is adopted. Wherein, the memory usually selects a high-speed Double-Data-Rate Synchronous Dynamic Random Access Memory (Double-Data-Rate Synchronous DRAM, DDR SDRAM). [0003] The address of the storage unit in DDR SDRAM consists of a three-dimensional address space: bank address, row address, and column address. DDR SDRAM is composed of multiple memory banks, and the data access between each memory bank is indep...

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Problems solved by technology

[0009] However, each processing module in the system-on-chip needs to exchange data with DDR SDRAM during operation, and the system requires high-performance DDR SDRAM. The method of controlling DDR SDRAM in the prior art has become a bottleneck restricting the development of the system-on-chip. The storage controller of the system is a hot spot in HDTV SOC design at present

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